| 1 |
2 |
robfinch |
// ============================================================================
|
| 2 |
|
|
// RAMCtrl.v
|
| 3 |
|
|
// - Interface to PSRAM
|
| 4 |
|
|
//
|
| 5 |
|
|
//
|
| 6 |
|
|
// 2010 Robert Finch
|
| 7 |
|
|
// robfinch<remove>@FPGAfield.ca
|
| 8 |
|
|
//
|
| 9 |
|
|
//
|
| 10 |
|
|
// This source code is available for evaluation and validation purposes
|
| 11 |
|
|
// only. This copyright statement and disclaimer must remain present in
|
| 12 |
|
|
// the file.
|
| 13 |
|
|
//
|
| 14 |
|
|
//
|
| 15 |
|
|
// NO WARRANTY.
|
| 16 |
|
|
// THIS Work, IS PROVIDEDED "AS IS" WITH NO WARRANTIES OF ANY KIND, WHETHER
|
| 17 |
|
|
// EXPRESS OR IMPLIED. The user must assume the entire risk of using the
|
| 18 |
|
|
// Work.
|
| 19 |
|
|
//
|
| 20 |
|
|
// IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
|
| 21 |
|
|
// INCIDENTAL, CONSEQUENTIAL, OR PUNITIVE DAMAGES WHATSOEVER RELATING TO
|
| 22 |
|
|
// THE USE OF THIS WORK, OR YOUR RELATIONSHIP WITH THE AUTHOR.
|
| 23 |
|
|
//
|
| 24 |
|
|
// IN ADDITION, IN NO EVENT DOES THE AUTHOR AUTHORIZE YOU TO USE THE WORK
|
| 25 |
|
|
// IN APPLICATIONS OR SYSTEMS WHERE THE WORK'S FAILURE TO PERFORM CAN
|
| 26 |
|
|
// REASONABLY BE EXPECTED TO RESULT IN A SIGNIFICANT PHYSICAL INJURY, OR IN
|
| 27 |
|
|
// LOSS OF LIFE. ANY SUCH USE BY YOU IS ENTIRELY AT YOUR OWN RISK, AND YOU
|
| 28 |
|
|
// AGREE TO HOLD THE AUTHOR AND CONTRIBUTORS HARMLESS FROM ANY CLAIMS OR
|
| 29 |
|
|
// LOSSES RELATING TO SUCH UNAUTHORIZED USE.
|
| 30 |
|
|
//
|
| 31 |
|
|
//
|
| 32 |
|
|
// Verilog 1995
|
| 33 |
|
|
// Webpack 9.2i xc3s1200-4fg320
|
| 34 |
|
|
// 177 slices / 339 LUTs / 107.262 MHz
|
| 35 |
|
|
// 120 ff's /
|
| 36 |
|
|
//
|
| 37 |
|
|
// ============================================================================
|
| 38 |
|
|
|
| 39 |
|
|
// 36/256 6/16
|
| 40 |
|
|
// 16x with only 6x
|
| 41 |
|
|
// 276 slices / 770 LUTs / 246 FF's / 119.446 MHz
|
| 42 |
|
|
|
| 43 |
|
|
module rtf68kSysRAMCtrl
|
| 44 |
|
|
(
|
| 45 |
|
|
rst_i, clk_i, gblen,
|
| 46 |
|
|
as, dtack, rw, uds, lds, adr, dat_i, dat_o,
|
| 47 |
|
|
eppWr, eppRd, eppAdr, eppDati, eppDato, eppHSreq, eppStart, eppDone,
|
| 48 |
|
|
vcti_i, vcyc_i, vack_o, vadr_i, vdat_o,
|
| 49 |
|
|
gr_cyc_i, gr_stb_i, gr_ack_o, gr_we_i, gr_sel_i, gr_adr_i, gr_dat_i, gr_dat_o,
|
| 50 |
|
|
sp_cyc_i, sp_stb_i, sp_ack_o, sp_we_i, sp_sel_i, sp_adr_i, sp_dat_i, sp_dat_o,
|
| 51 |
|
|
ar_cyc_i, ar_stb_i, ar_ack_o, ar_we_i, ar_sel_i, ar_adr_i, ar_dat_i, ar_dat_o,
|
| 52 |
|
|
ap_cyc_i, ap_stb_i, ap_ack_o, ap_we_i, ap_sel_i, ap_adr_i, ap_dat_i, ap_dat_o,
|
| 53 |
|
|
ram_clk, ram_adv, ram_cre, ram_ce, ram_we, ram_oe, ram_lb, ram_ub, ram_a, ram_d, ram_weh,
|
| 54 |
|
|
flash_ce, flash_st, flash_rp
|
| 55 |
|
|
);
|
| 56 |
|
|
parameter pClkFreq = 60000000;
|
| 57 |
|
|
parameter ABIT=24;
|
| 58 |
|
|
// timing parameters must be at least 1
|
| 59 |
|
|
parameter tRC = pClkFreq / 14285714 + 1; // 70 ns
|
| 60 |
|
|
parameter tWC = pClkFreq / 14285714 + 1; // 70 ns
|
| 61 |
|
|
parameter tAPA = pClkFreq / 50000000 + 1; // 20 ns page mode access time
|
| 62 |
|
|
parameter tPWR = pClkFreq / 6667 + 1; // 150 micro seconds
|
| 63 |
|
|
parameter pRCRValue = 23'h000090; // enables page mode (default setting 0010
|
| 64 |
|
|
parameter pBCRValue = 23'h089D1F;
|
| 65 |
|
|
parameter tRCFlash = pClkFreq / 9090909 + 1; // 110 ns
|
| 66 |
|
|
|
| 67 |
|
|
// states
|
| 68 |
|
|
parameter POWER_UP = 6'd0;
|
| 69 |
|
|
parameter WRITE_RCR = 6'd1;
|
| 70 |
|
|
parameter WRITE_RCR_WAIT = 6'd2;
|
| 71 |
|
|
parameter WRITE_BCR = 6'd3;
|
| 72 |
|
|
parameter WRITE_BCR_WAIT = 6'd4;
|
| 73 |
|
|
parameter IDLE = 6'd5;
|
| 74 |
|
|
parameter CPU_ACCESS = 6'd6;
|
| 75 |
|
|
parameter CPU_ACCESS1 = 6'd7;
|
| 76 |
|
|
parameter CPU_NACK = 6'd8;
|
| 77 |
|
|
parameter WAIT_NACK = 6'd9;
|
| 78 |
|
|
parameter STORE_WAIT = 6'd12;
|
| 79 |
|
|
parameter FETCH_VIDEO = 6'd13;
|
| 80 |
|
|
parameter FV1 = 6'd14;
|
| 81 |
|
|
parameter FV2 = 6'd15;
|
| 82 |
|
|
parameter FV_NACK = 6'd16;
|
| 83 |
|
|
parameter RANDOMIZE = 6'd17;
|
| 84 |
|
|
parameter RANDOMIZE2 = 6'd18;
|
| 85 |
|
|
|
| 86 |
|
|
parameter EPP_STORE = 6'd21;
|
| 87 |
|
|
parameter EPP_FETCH = 6'd22;
|
| 88 |
|
|
parameter EPP_NACK = 6'd23;
|
| 89 |
|
|
|
| 90 |
|
|
parameter CPU_STORE = 6'd24;
|
| 91 |
|
|
parameter CPU_STORE2 = 6'd25;
|
| 92 |
|
|
parameter CST_NACK = 6'd26;
|
| 93 |
|
|
|
| 94 |
|
|
parameter AP_FETCH = 6'd27;
|
| 95 |
|
|
parameter AP_NACK = 6'd28;
|
| 96 |
|
|
parameter GR_ACCESS = 6'd29;
|
| 97 |
|
|
parameter GR_NACK = 6'd30;
|
| 98 |
|
|
parameter SP_ACCESS = 6'd31;
|
| 99 |
|
|
parameter SP_NACK = 6'd32;
|
| 100 |
|
|
|
| 101 |
|
|
parameter WB_CAB=3'b001; // constant address burst
|
| 102 |
|
|
parameter WB_BURST=3'b010; // incrementing burst cycle
|
| 103 |
|
|
parameter WB_EOB=3'b111; // end-of-burst
|
| 104 |
|
|
|
| 105 |
|
|
// SYSCON
|
| 106 |
|
|
input rst_i; // system reset
|
| 107 |
|
|
input clk_i; // system clock
|
| 108 |
|
|
input gblen;
|
| 109 |
|
|
// Slave
|
| 110 |
|
|
input as; // cycle valid
|
| 111 |
|
|
output dtack; // transfer acknowledge
|
| 112 |
|
|
input rw; // write enable
|
| 113 |
|
|
input uds;
|
| 114 |
|
|
input lds;
|
| 115 |
|
|
input [43:0] adr; // address
|
| 116 |
|
|
input [15:0] dat_i; // data input
|
| 117 |
|
|
output [15:0] dat_o; // data output
|
| 118 |
|
|
// Epp interface
|
| 119 |
|
|
input eppWr;
|
| 120 |
|
|
input eppRd;
|
| 121 |
|
|
input [7:0] eppAdr;
|
| 122 |
|
|
input [7:0] eppDati;
|
| 123 |
|
|
output [7:0] eppDato;
|
| 124 |
|
|
reg [7:0] eppDato;
|
| 125 |
|
|
output eppHSreq;
|
| 126 |
|
|
output eppDone;
|
| 127 |
|
|
input eppStart;
|
| 128 |
|
|
// WISHBONE Slave
|
| 129 |
|
|
input [2:0] vcti_i;
|
| 130 |
|
|
input vcyc_i;
|
| 131 |
|
|
output vack_o;
|
| 132 |
|
|
input [23:0] vadr_i;
|
| 133 |
|
|
output [15:0] vdat_o;
|
| 134 |
|
|
// WISHBONE Slave
|
| 135 |
|
|
input gr_cyc_i; // cycle valid
|
| 136 |
|
|
input gr_stb_i; // strobe
|
| 137 |
|
|
output gr_ack_o; // transfer acknowledge
|
| 138 |
|
|
input gr_we_i; // write enable
|
| 139 |
|
|
input [ 1:0] gr_sel_i; // byte select
|
| 140 |
|
|
input [31:0] gr_adr_i; // address
|
| 141 |
|
|
input [15:0] gr_dat_i; // data input
|
| 142 |
|
|
output [15:0] gr_dat_o; // data output
|
| 143 |
|
|
reg [15:0] gr_dat_o;
|
| 144 |
|
|
// WISHBONE Slave
|
| 145 |
|
|
input sp_cyc_i; // cycle valid
|
| 146 |
|
|
input sp_stb_i; // strobe
|
| 147 |
|
|
output sp_ack_o; // transfer acknowledge
|
| 148 |
|
|
input sp_we_i; // write enable
|
| 149 |
|
|
input [ 1:0] sp_sel_i; // byte select
|
| 150 |
|
|
input [31:0] sp_adr_i; // address
|
| 151 |
|
|
input [15:0] sp_dat_i; // data input
|
| 152 |
|
|
output [15:0] sp_dat_o; // data output
|
| 153 |
|
|
reg [15:0] sp_dat_o;
|
| 154 |
|
|
// WISHBONE Slave
|
| 155 |
|
|
input ar_cyc_i; // cycle valid
|
| 156 |
|
|
input ar_stb_i; // strobe
|
| 157 |
|
|
output ar_ack_o; // transfer acknowledge
|
| 158 |
|
|
input ar_we_i; // write enable
|
| 159 |
|
|
input [ 1:0] ar_sel_i; // byte select
|
| 160 |
|
|
input [43:0] ar_adr_i; // address
|
| 161 |
|
|
input [15:0] ar_dat_i; // data input
|
| 162 |
|
|
output [15:0] ar_dat_o; // data output
|
| 163 |
|
|
// WISHBONE Slave
|
| 164 |
|
|
input ap_cyc_i; // cycle valid
|
| 165 |
|
|
input ap_stb_i; // strobe
|
| 166 |
|
|
output ap_ack_o; // transfer acknowledge
|
| 167 |
|
|
input ap_we_i; // write enable
|
| 168 |
|
|
input [ 1:0] ap_sel_i; // byte select
|
| 169 |
|
|
input [43:0] ap_adr_i; // address
|
| 170 |
|
|
input [15:0] ap_dat_i; // data input
|
| 171 |
|
|
output [15:0] ap_dat_o; // data output
|
| 172 |
|
|
// RAM ports
|
| 173 |
|
|
output ram_clk;
|
| 174 |
|
|
tri ram_clk;
|
| 175 |
|
|
output ram_adv;
|
| 176 |
|
|
tri ram_adv;
|
| 177 |
|
|
output ram_cre;
|
| 178 |
|
|
tri ram_cre;
|
| 179 |
|
|
output ram_ce;
|
| 180 |
|
|
tri ram_ce;
|
| 181 |
|
|
output ram_we;
|
| 182 |
|
|
tri ram_we;
|
| 183 |
|
|
output ram_weh;
|
| 184 |
|
|
tri ram_weh;
|
| 185 |
|
|
output ram_oe;
|
| 186 |
|
|
tri ram_oe;
|
| 187 |
|
|
output ram_lb;
|
| 188 |
|
|
tri ram_lb;
|
| 189 |
|
|
output ram_ub;
|
| 190 |
|
|
tri ram_ub;
|
| 191 |
|
|
output [23:1] ram_a;
|
| 192 |
|
|
tri [23:1] ram_a;
|
| 193 |
|
|
inout [15:0] ram_d;
|
| 194 |
|
|
tri [15:0] ram_d;
|
| 195 |
|
|
output flash_ce;
|
| 196 |
|
|
tri flash_ce;
|
| 197 |
|
|
output flash_rp;
|
| 198 |
|
|
tri flash_rp;
|
| 199 |
|
|
input flash_st;
|
| 200 |
|
|
|
| 201 |
|
|
reg iram_cre;
|
| 202 |
|
|
reg iram_ce;
|
| 203 |
|
|
reg iram_we;
|
| 204 |
|
|
reg iram_oe;
|
| 205 |
|
|
reg iram_lb;
|
| 206 |
|
|
reg iram_ub;
|
| 207 |
|
|
reg iram_weh;
|
| 208 |
|
|
reg [23:1] iram_a;
|
| 209 |
|
|
reg [15:0] rdat;
|
| 210 |
|
|
|
| 211 |
|
|
reg iflash_ce;
|
| 212 |
|
|
|
| 213 |
|
|
assign ram_clk = gblen ? 1'b0 : 1'bz; // always low
|
| 214 |
|
|
assign ram_adv = gblen ? 1'b0 : 1'bz; // always low - asynch mode
|
| 215 |
|
|
|
| 216 |
|
|
reg [22:0] BCRReg;
|
| 217 |
|
|
reg [22:0] RCRReg;
|
| 218 |
|
|
|
| 219 |
|
|
wire pud;
|
| 220 |
|
|
reg gack;
|
| 221 |
|
|
|
| 222 |
|
|
reg [15:0] vdat_o;
|
| 223 |
|
|
reg [15:0] dat_o;
|
| 224 |
|
|
reg [15:0] ap_dat_o;
|
| 225 |
|
|
reg vack1_o;
|
| 226 |
|
|
reg ap_ack_o;
|
| 227 |
|
|
reg ar_ack_o;
|
| 228 |
|
|
assign vack_o = vack1_o & vcyc_i;
|
| 229 |
|
|
|
| 230 |
|
|
assign ram_d = (gblen && (iram_weh==1'b0)) ? rdat : {16{1'bz}};
|
| 231 |
|
|
|
| 232 |
|
|
wire isCPUAccess = !as & (!uds | !lds);
|
| 233 |
|
|
wire isVideoRead = vcyc_i;
|
| 234 |
|
|
wire isARWrite = ar_cyc_i && ar_stb_i && ar_we_i && (ar_adr_i[43:24]==20'h00);
|
| 235 |
|
|
wire isAPRead = ap_cyc_i && ap_stb_i && (ap_adr_i[43:24]==20'h00);
|
| 236 |
|
|
|
| 237 |
|
|
// Forces ack_o low immediately when cyc_i or stb_i is lost.
|
| 238 |
|
|
reg dtack1;
|
| 239 |
|
|
assign dtack = (uds & lds) | dtack1;
|
| 240 |
|
|
|
| 241 |
|
|
reg gack1;
|
| 242 |
|
|
assign gr_ack_o = gack1 & gr_cyc_i & gr_stb_i;
|
| 243 |
|
|
reg spack;
|
| 244 |
|
|
assign sp_ack_o = spack & sp_cyc_i & sp_stb_i;
|
| 245 |
|
|
|
| 246 |
|
|
reg [31:0] sadr;
|
| 247 |
|
|
reg [15:0] sdat;
|
| 248 |
|
|
reg [1:0] ssel;
|
| 249 |
|
|
reg [2:0] src;
|
| 250 |
|
|
reg [7:0] vhold;
|
| 251 |
|
|
|
| 252 |
|
|
reg [7:0] cnt;
|
| 253 |
|
|
wire cnt_done = cnt==8'd0;
|
| 254 |
|
|
wire flash = adr[31:24]==8'hFE;
|
| 255 |
|
|
assign iflash_rp = rst_i;
|
| 256 |
|
|
|
| 257 |
|
|
reg [ 5:0] state;
|
| 258 |
|
|
reg [7:0] ectl;
|
| 259 |
|
|
reg [23:0] eadr;
|
| 260 |
|
|
assign eppDone = state==EPP_NACK;
|
| 261 |
|
|
assign eppHSreq = eppAdr==8'h0E || eppAdr==8'h0F;
|
| 262 |
|
|
wire eppCycle = (eppAdr==8'h0E || eppAdr==8'h0F) && eppStart;
|
| 263 |
|
|
reg [15:0] edat,edato;
|
| 264 |
|
|
wire eword = ectl[5];
|
| 265 |
|
|
wire eppDudCycle = (!(ectl[0] ^ eadr[0])) && eword; // read odd, write even
|
| 266 |
|
|
|
| 267 |
|
|
assign ram_cre = gblen ? iram_cre : 1'bz;
|
| 268 |
|
|
assign ram_ce = gblen ? iram_ce : 1'bz;
|
| 269 |
|
|
assign ram_we = gblen ? iram_we : 1'bz;
|
| 270 |
|
|
assign ram_oe = gblen ? iram_oe : 1'bz;
|
| 271 |
|
|
assign ram_weh = gblen ? iram_weh : 1'bz;
|
| 272 |
|
|
assign ram_ub = gblen ? iram_ub : 1'bz;
|
| 273 |
|
|
assign ram_lb = gblen ? iram_lb : 1'bz;
|
| 274 |
|
|
assign ram_a = gblen ? iram_a : {23{1'bz}};
|
| 275 |
|
|
assign flash_ce = gblen ? iflash_ce : 1'bz;
|
| 276 |
|
|
assign flash_rp = gblen ? iflash_rp : 1'bz;
|
| 277 |
|
|
|
| 278 |
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
| 279 |
|
|
// Epp register reads
|
| 280 |
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
| 281 |
|
|
|
| 282 |
|
|
always @(eppAdr)
|
| 283 |
|
|
case(eppAdr)
|
| 284 |
|
|
8'h08: eppDato <= ectl;
|
| 285 |
|
|
8'h09: eppDato <= eadr[ 7: 0];
|
| 286 |
|
|
8'h0A: eppDato <= eadr[15: 8];
|
| 287 |
|
|
8'h0B: eppDato <= eadr[23:16];
|
| 288 |
|
|
8'h0C: eppDato <= edato[7:0];
|
| 289 |
|
|
8'h0D: eppDato <= eadr[0] ? ram_d[15:8] : ram_d[7:0];
|
| 290 |
|
|
8'h0E: eppDato <= edato[7:0];
|
| 291 |
|
|
default: eppDato <= 8'h00; // prepare for wor
|
| 292 |
|
|
endcase
|
| 293 |
|
|
|
| 294 |
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
| 295 |
|
|
// Probably not necessary, but who knows ?
|
| 296 |
|
|
// FPGA's typically have an internal power up delay, which is likely
|
| 297 |
|
|
// greater than the RAM's.
|
| 298 |
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
| 299 |
|
|
PSRAMCtrl_PudTimer u7 (rst_i, clk_i, pud);
|
| 300 |
|
|
|
| 301 |
|
|
always @(posedge clk_i)
|
| 302 |
|
|
if (rst_i) begin
|
| 303 |
|
|
BCRReg <= pBCRValue;
|
| 304 |
|
|
RCRReg <= pRCRValue;
|
| 305 |
|
|
end
|
| 306 |
|
|
|
| 307 |
|
|
reg [15:0] radr;
|
| 308 |
|
|
|
| 309 |
|
|
always @(posedge clk_i)
|
| 310 |
|
|
if (rst_i) begin
|
| 311 |
|
|
iram_cre <= 1'b0;
|
| 312 |
|
|
iram_ce <= 1'b1;
|
| 313 |
|
|
iram_we <= 1'b1;
|
| 314 |
|
|
iram_weh <= 1'b1;
|
| 315 |
|
|
iram_oe <= 1'b1;
|
| 316 |
|
|
iram_lb <= 1'b1;
|
| 317 |
|
|
iram_ub <= 1'b1;
|
| 318 |
|
|
iram_a <= 23'h7FFFFF;
|
| 319 |
|
|
iflash_ce <= 1'b1;
|
| 320 |
|
|
vack1_o <= 1'b0;
|
| 321 |
|
|
ar_ack_o <= 1'b0;
|
| 322 |
|
|
ap_ack_o <= 1'b0;
|
| 323 |
|
|
dtack1 <= 1'b1;
|
| 324 |
|
|
gack1 <= 1'b0;
|
| 325 |
|
|
dat_o <= 16'hFFFF;
|
| 326 |
|
|
state <= POWER_UP;
|
| 327 |
|
|
radr <= 16'h0000;
|
| 328 |
|
|
rdat <= 32'h0000_0000;
|
| 329 |
|
|
edato <= 16'h8765;
|
| 330 |
|
|
end
|
| 331 |
|
|
else begin
|
| 332 |
|
|
|
| 333 |
|
|
// Downcount the RAM access timing counter
|
| 334 |
|
|
if (!cnt_done)
|
| 335 |
|
|
cnt <= cnt - 8'd1;
|
| 336 |
|
|
|
| 337 |
|
|
// Clear bus transfer acknowledge
|
| 338 |
|
|
if (!ar_cyc_i || !ar_stb_i)
|
| 339 |
|
|
ar_ack_o <= 1'b0;
|
| 340 |
|
|
|
| 341 |
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
| 342 |
|
|
// Epp control register access
|
| 343 |
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
| 344 |
|
|
//
|
| 345 |
|
|
if (eppWr) begin
|
| 346 |
|
|
case(eppAdr)
|
| 347 |
|
|
8'h08: begin
|
| 348 |
|
|
ectl <= eppDati;
|
| 349 |
|
|
end
|
| 350 |
|
|
8'h09: eadr[7:0] <= eppDati;
|
| 351 |
|
|
8'h0A: eadr[15:8] <= eppDati;
|
| 352 |
|
|
8'h0B: eadr[23:16] <= eppDati;
|
| 353 |
|
|
8'h0C: if (eadr[0])
|
| 354 |
|
|
edat[15:8] <= eppDati;
|
| 355 |
|
|
else
|
| 356 |
|
|
edat[7:0] <= eppDati;
|
| 357 |
|
|
8'h0E,8'h0F:
|
| 358 |
|
|
begin
|
| 359 |
|
|
if (eadr[0])
|
| 360 |
|
|
edat[15:8] <= eppDati;
|
| 361 |
|
|
else
|
| 362 |
|
|
edat[7:0] <= eppDati;
|
| 363 |
|
|
end
|
| 364 |
|
|
endcase
|
| 365 |
|
|
end
|
| 366 |
|
|
|
| 367 |
|
|
case(state)
|
| 368 |
|
|
|
| 369 |
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
| 370 |
|
|
// Power-up
|
| 371 |
|
|
//
|
| 372 |
|
|
// Don't do anything for 150 micro-seconds.
|
| 373 |
|
|
// Then set the RAM's control registers as desired.
|
| 374 |
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
| 375 |
|
|
POWER_UP:
|
| 376 |
|
|
if (!pud)
|
| 377 |
|
|
state <= WRITE_RCR;
|
| 378 |
|
|
|
| 379 |
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
| 380 |
|
|
// Wait for a read or write access request.
|
| 381 |
|
|
// Dispatch
|
| 382 |
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
| 383 |
|
|
IDLE:
|
| 384 |
|
|
begin
|
| 385 |
|
|
cnt <= tRC; // read access time (70ns)
|
| 386 |
|
|
// Drive the RAM control signals inactive then
|
| 387 |
|
|
// override them later.
|
| 388 |
|
|
iram_ce <= 1'b1;
|
| 389 |
|
|
iram_oe <= 1'b1;
|
| 390 |
|
|
iram_we <= 1'b1;
|
| 391 |
|
|
iram_weh <= 1'b1;
|
| 392 |
|
|
iram_ub <= 1'b1;
|
| 393 |
|
|
iram_lb <= 1'b1;
|
| 394 |
|
|
iflash_ce <= 1'b1;
|
| 395 |
|
|
|
| 396 |
|
|
// We can only get out of the IDLE state if the global
|
| 397 |
|
|
// enable signal is active.
|
| 398 |
|
|
//
|
| 399 |
|
|
if (!gblen)
|
| 400 |
|
|
;
|
| 401 |
|
|
// Wait for flash to be ready.
|
| 402 |
|
|
else if (!flash_st)
|
| 403 |
|
|
;
|
| 404 |
|
|
|
| 405 |
|
|
// Page align video address
|
| 406 |
|
|
else if (isVideoRead) begin
|
| 407 |
|
|
state <= FETCH_VIDEO;
|
| 408 |
|
|
iram_ce <= 1'b0;
|
| 409 |
|
|
iram_oe <= 1'b0;
|
| 410 |
|
|
iram_ub <= 1'b0;
|
| 411 |
|
|
iram_lb <= 1'b0;
|
| 412 |
|
|
iram_a <= vadr_i[23:1];
|
| 413 |
|
|
end
|
| 414 |
|
|
/*
|
| 415 |
|
|
else if (isARWrite) begin
|
| 416 |
|
|
state <= STORE_WAIT;
|
| 417 |
|
|
ram_ce <= 1'b0;
|
| 418 |
|
|
ram_we <= 1'b0;
|
| 419 |
|
|
ram_oe <= 1'b1;
|
| 420 |
|
|
ram_ub <= 1'b0;
|
| 421 |
|
|
ram_lb <= 1'b0;
|
| 422 |
|
|
ram_a <= ar_adr_i[23:1];
|
| 423 |
|
|
rdat <= ar_dat_i;
|
| 424 |
|
|
src <= 3'd0;
|
| 425 |
|
|
end
|
| 426 |
|
|
*/
|
| 427 |
|
|
// Teh data strobes may not be active yet. They become
|
| 428 |
|
|
// active a cycle after the address strobe.
|
| 429 |
|
|
else if (!as) begin
|
| 430 |
|
|
state <= CPU_ACCESS;
|
| 431 |
|
|
if (flash)
|
| 432 |
|
|
cnt <= tRCFlash;
|
| 433 |
|
|
iram_a <= adr[23:1];
|
| 434 |
|
|
iram_ce <= !(adr[31:24]==8'h00);
|
| 435 |
|
|
iflash_ce <= !(adr[31:24]==8'hFE);
|
| 436 |
|
|
iram_oe <= !rw;
|
| 437 |
|
|
iram_we <= rw || (adr[31:24]==8'hFE);
|
| 438 |
|
|
iram_weh <= rw;
|
| 439 |
|
|
iram_ub <= uds;
|
| 440 |
|
|
iram_lb <= lds;
|
| 441 |
|
|
rdat <= dat_i;
|
| 442 |
|
|
end
|
| 443 |
|
|
else if (gr_cyc_i) begin
|
| 444 |
|
|
state <= GR_ACCESS;
|
| 445 |
|
|
iram_a <= gr_adr_i[23:1];
|
| 446 |
|
|
iram_ce <= 1'b0;
|
| 447 |
|
|
iram_oe <= gr_we_i;
|
| 448 |
|
|
iram_we <= !gr_we_i;
|
| 449 |
|
|
iram_weh <= !gr_we_i;
|
| 450 |
|
|
iram_ub <= gr_sel_i[1];
|
| 451 |
|
|
iram_lb <= gr_sel_i[0];
|
| 452 |
|
|
rdat <= gr_dat_i;
|
| 453 |
|
|
end
|
| 454 |
|
|
else if (sp_cyc_i) begin
|
| 455 |
|
|
state <= SP_ACCESS;
|
| 456 |
|
|
iram_a <= sp_adr_i[23:1];
|
| 457 |
|
|
iram_ce <= 1'b0;
|
| 458 |
|
|
iram_oe <= sp_we_i;
|
| 459 |
|
|
iram_we <= !sp_we_i;
|
| 460 |
|
|
iram_weh <= !sp_we_i;
|
| 461 |
|
|
iram_ub <= sp_sel_i[1];
|
| 462 |
|
|
iram_lb <= sp_sel_i[0];
|
| 463 |
|
|
rdat <= sp_dat_i;
|
| 464 |
|
|
end
|
| 465 |
|
|
else if (isAPRead) begin
|
| 466 |
|
|
state <= AP_FETCH;
|
| 467 |
|
|
iram_ce <= 1'b0;
|
| 468 |
|
|
iram_oe <= 1'b0;
|
| 469 |
|
|
iram_ub <= 1'b0;
|
| 470 |
|
|
iram_lb <= 1'b0;
|
| 471 |
|
|
iram_a <= ap_adr_i;
|
| 472 |
|
|
src <= 3'd2;
|
| 473 |
|
|
end
|
| 474 |
|
|
else if (eppCycle) begin
|
| 475 |
|
|
if (eppDudCycle) begin
|
| 476 |
|
|
edato[7:0] <= edato[15:8];
|
| 477 |
|
|
state <= EPP_NACK;
|
| 478 |
|
|
end
|
| 479 |
|
|
else begin
|
| 480 |
|
|
cnt <= tRC; // read (or write) access time (70ns)
|
| 481 |
|
|
iram_oe <= !ectl[0];
|
| 482 |
|
|
iram_we <= ectl[0];
|
| 483 |
|
|
iram_weh <= ectl[0];
|
| 484 |
|
|
iram_ce <= 1'b0;
|
| 485 |
|
|
iram_a <= eadr[23:1];
|
| 486 |
|
|
if (eword) begin
|
| 487 |
|
|
iram_lb <= 1'b0;
|
| 488 |
|
|
iram_ub <= 1'b0;
|
| 489 |
|
|
end
|
| 490 |
|
|
else begin
|
| 491 |
|
|
iram_lb <= eadr[0];
|
| 492 |
|
|
iram_ub <= !eadr[0];
|
| 493 |
|
|
end
|
| 494 |
|
|
rdat <= edat;
|
| 495 |
|
|
state <= ectl[0] ? EPP_FETCH : EPP_STORE;
|
| 496 |
|
|
end
|
| 497 |
|
|
end
|
| 498 |
|
|
end
|
| 499 |
|
|
|
| 500 |
|
|
|
| 501 |
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
| 502 |
|
|
// Memory Fetch/Store completion
|
| 503 |
|
|
// - If the address is still on the same page, use page mode timing
|
| 504 |
|
|
// - Terminate the write cycle to the RAM as soon as access time
|
| 505 |
|
|
// is met by driving ram_we high (inactive).
|
| 506 |
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
| 507 |
|
|
CPU_ACCESS:
|
| 508 |
|
|
// Wait for a data strobe to go active (low)
|
| 509 |
|
|
if (~lds | ~uds) begin
|
| 510 |
|
|
cnt <= rw ? tRC : tWC;
|
| 511 |
|
|
state <= CPU_ACCESS1;
|
| 512 |
|
|
iram_a <= adr[23:1];
|
| 513 |
|
|
iram_ce <= 1'b0;
|
| 514 |
|
|
iram_oe <= ~rw;
|
| 515 |
|
|
iram_we <= rw || (adr[31:24]==8'hFE);
|
| 516 |
|
|
iram_weh <= rw;
|
| 517 |
|
|
iram_ub <= uds;
|
| 518 |
|
|
iram_lb <= lds;
|
| 519 |
|
|
rdat <= dat_i;
|
| 520 |
|
|
end
|
| 521 |
|
|
|
| 522 |
|
|
CPU_ACCESS1:
|
| 523 |
|
|
if (cnt_done) begin
|
| 524 |
|
|
iram_we <= 1'b1; // cause a rising edge on we
|
| 525 |
|
|
dat_o <= ram_d;
|
| 526 |
|
|
dtack1 <= 1'b0;
|
| 527 |
|
|
state <= CPU_NACK;
|
| 528 |
|
|
end
|
| 529 |
|
|
|
| 530 |
|
|
CPU_NACK:
|
| 531 |
|
|
// Wait for both data strobes to go inactive (high)
|
| 532 |
|
|
// The address strobe should also go high at this point,
|
| 533 |
|
|
// unless it's an RMW cycle.
|
| 534 |
|
|
if (uds & lds) begin
|
| 535 |
|
|
dtack1 <= 1'b1;
|
| 536 |
|
|
iram_ce <= 1'b1;
|
| 537 |
|
|
iram_oe <= 1'b1;
|
| 538 |
|
|
iram_we <= 1'b1;
|
| 539 |
|
|
iram_weh <= 1'b1;
|
| 540 |
|
|
iram_lb <= 1'b1;
|
| 541 |
|
|
iram_ub <= 1'b1;
|
| 542 |
|
|
if (as)
|
| 543 |
|
|
state <= IDLE;
|
| 544 |
|
|
// Must be a RMW (read-modify-write) cycle
|
| 545 |
|
|
// Or a longword access
|
| 546 |
|
|
// go back for another access
|
| 547 |
|
|
else
|
| 548 |
|
|
state <= CPU_ACCESS;
|
| 549 |
|
|
end
|
| 550 |
|
|
|
| 551 |
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
| 552 |
|
|
//
|
| 553 |
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
| 554 |
|
|
GR_ACCESS:
|
| 555 |
|
|
if (cnt_done) begin
|
| 556 |
|
|
iram_we <= 1'b1;
|
| 557 |
|
|
gr_dat_o <= ram_d;
|
| 558 |
|
|
gack1 <= 1'b1;
|
| 559 |
|
|
state <= GR_NACK;
|
| 560 |
|
|
end
|
| 561 |
|
|
GR_NACK:
|
| 562 |
|
|
if (!gr_cyc_i || !gr_stb_i) begin
|
| 563 |
|
|
gack1 <= 1'b0;
|
| 564 |
|
|
iram_ce <= 1'b1;
|
| 565 |
|
|
iram_oe <= 1'b1;
|
| 566 |
|
|
iram_we <= 1'b1;
|
| 567 |
|
|
iram_weh <= 1'b1;
|
| 568 |
|
|
iram_lb <= 1'b1;
|
| 569 |
|
|
iram_ub <= 1'b1;
|
| 570 |
|
|
state <= IDLE;
|
| 571 |
|
|
end
|
| 572 |
|
|
|
| 573 |
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
| 574 |
|
|
//
|
| 575 |
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
| 576 |
|
|
SP_ACCESS:
|
| 577 |
|
|
if (cnt_done) begin
|
| 578 |
|
|
iram_we <= 1'b1;
|
| 579 |
|
|
sp_dat_o <= ram_d;
|
| 580 |
|
|
spack <= 1'b1;
|
| 581 |
|
|
state <= SP_NACK;
|
| 582 |
|
|
end
|
| 583 |
|
|
SP_NACK:
|
| 584 |
|
|
if (!sp_cyc_i || !sp_stb_i) begin
|
| 585 |
|
|
spack <= 1'b0;
|
| 586 |
|
|
iram_ce <= 1'b1;
|
| 587 |
|
|
iram_oe <= 1'b1;
|
| 588 |
|
|
iram_we <= 1'b1;
|
| 589 |
|
|
iram_weh <= 1'b1;
|
| 590 |
|
|
iram_lb <= 1'b1;
|
| 591 |
|
|
iram_ub <= 1'b1;
|
| 592 |
|
|
state <= IDLE;
|
| 593 |
|
|
end
|
| 594 |
|
|
|
| 595 |
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
| 596 |
|
|
//
|
| 597 |
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
| 598 |
|
|
AP_FETCH:
|
| 599 |
|
|
if (cnt_done) begin
|
| 600 |
|
|
ap_dat_o <= ram_d;
|
| 601 |
|
|
ap_ack_o <= 1'b1;
|
| 602 |
|
|
state <= AP_NACK;
|
| 603 |
|
|
end
|
| 604 |
|
|
AP_NACK:
|
| 605 |
|
|
if (!ap_cyc_i || !ap_stb_i) begin
|
| 606 |
|
|
ap_ack_o <= 1'b0;
|
| 607 |
|
|
iram_ce <= 1'b1;
|
| 608 |
|
|
iram_oe <= 1'b1;
|
| 609 |
|
|
iram_we <= 1'b1;
|
| 610 |
|
|
iram_weh <= 1'b1;
|
| 611 |
|
|
iram_lb <= 1'b1;
|
| 612 |
|
|
iram_ub <= 1'b1;
|
| 613 |
|
|
state <= IDLE;
|
| 614 |
|
|
end
|
| 615 |
|
|
|
| 616 |
|
|
|
| 617 |
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
| 618 |
|
|
// Fetch video data using page mode access.
|
| 619 |
|
|
// A whole memory page of 32 bytes is fetched.
|
| 620 |
|
|
// Typically 5+30 = 35 clock cycles are required assuming a
|
| 621 |
|
|
// 60 MHz clock.
|
| 622 |
|
|
// 2+15+1 = 18 clock cycles @ 25 MHz
|
| 623 |
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
| 624 |
|
|
FETCH_VIDEO:
|
| 625 |
|
|
if (cnt_done) begin
|
| 626 |
|
|
vack1_o <= 1'b1;
|
| 627 |
|
|
vdat_o <= ram_d;
|
| 628 |
|
|
iram_a <= iram_a + 23'd1;
|
| 629 |
|
|
if (iram_a[4:1]==4'hF)
|
| 630 |
|
|
state <= FV_NACK;
|
| 631 |
|
|
end
|
| 632 |
|
|
else
|
| 633 |
|
|
vack1_o <= 1'b0;
|
| 634 |
|
|
|
| 635 |
|
|
FV_NACK:
|
| 636 |
|
|
if (!vcyc_i) begin
|
| 637 |
|
|
vack1_o <= 1'b0;
|
| 638 |
|
|
iram_ce <= 1'b1;
|
| 639 |
|
|
iram_oe <= 1'b1;
|
| 640 |
|
|
iram_we <= 1'b1;
|
| 641 |
|
|
iram_weh <= 1'b1;
|
| 642 |
|
|
iram_lb <= 1'b1;
|
| 643 |
|
|
iram_ub <= 1'b1;
|
| 644 |
|
|
state <= IDLE;
|
| 645 |
|
|
end
|
| 646 |
|
|
|
| 647 |
|
|
|
| 648 |
|
|
|
| 649 |
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
| 650 |
|
|
// Epp access states.
|
| 651 |
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
| 652 |
|
|
EPP_STORE:
|
| 653 |
|
|
if (cnt_done) begin
|
| 654 |
|
|
iram_we <= 1'b1;
|
| 655 |
|
|
state <= EPP_NACK;
|
| 656 |
|
|
end
|
| 657 |
|
|
EPP_FETCH:
|
| 658 |
|
|
if (cnt_done) begin
|
| 659 |
|
|
edato <= ram_d;
|
| 660 |
|
|
state <= EPP_NACK;
|
| 661 |
|
|
end
|
| 662 |
|
|
EPP_NACK:
|
| 663 |
|
|
begin
|
| 664 |
|
|
if (eppCycle==1'b0) begin
|
| 665 |
|
|
iram_ce <= 1'b1;
|
| 666 |
|
|
iram_oe <= 1'b1;
|
| 667 |
|
|
iram_we <= 1'b1;
|
| 668 |
|
|
iram_weh <= 1'b1;
|
| 669 |
|
|
iram_lb <= 1'b1;
|
| 670 |
|
|
iram_ub <= 1'b1;
|
| 671 |
|
|
state <= IDLE;
|
| 672 |
|
|
eadr <= eadr + 23'd1;
|
| 673 |
|
|
end
|
| 674 |
|
|
end
|
| 675 |
|
|
|
| 676 |
|
|
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
| 677 |
|
|
// Memory randomizer.
|
| 678 |
|
|
// - On power up memory is usually filled with zeros, as a result the
|
| 679 |
|
|
// display appears blank and one can't tell whether or not the video
|
| 680 |
|
|
// (or perhaps anything else) is actually working.
|
| 681 |
|
|
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
| 682 |
|
|
|
| 683 |
|
|
RANDOMIZE:
|
| 684 |
|
|
begin
|
| 685 |
|
|
state <= RANDOMIZE2;
|
| 686 |
|
|
iram_ce <= 1'b0;
|
| 687 |
|
|
iram_oe <= 1'b1;
|
| 688 |
|
|
iram_we <= 1'b0;
|
| 689 |
|
|
iram_lb <= 1'b0;
|
| 690 |
|
|
iram_ub <= 1'b0;
|
| 691 |
|
|
iram_a <= iram_a + 23'd1;
|
| 692 |
|
|
rdat <= rdat * 17'h10DCD + 32'h1;
|
| 693 |
|
|
// rdat <= 16'hE003;
|
| 694 |
|
|
// rdat <= {2{ram_a[8:6],ram_a[8:6],ram_a[8:7]}};
|
| 695 |
|
|
cnt <= tWC;
|
| 696 |
|
|
end
|
| 697 |
|
|
RANDOMIZE2:
|
| 698 |
|
|
if (cnt_done) begin
|
| 699 |
|
|
if (iram_a==23'h7F_FFFF)
|
| 700 |
|
|
state <= IDLE;
|
| 701 |
|
|
else
|
| 702 |
|
|
state <= RANDOMIZE;
|
| 703 |
|
|
iram_ce <= 1'b1;
|
| 704 |
|
|
iram_we <= 1'b1;
|
| 705 |
|
|
end
|
| 706 |
|
|
|
| 707 |
|
|
|
| 708 |
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
| 709 |
|
|
// Write to the RAM's control registers
|
| 710 |
|
|
// RCR: enables page mode (default setting 0010
|
| 711 |
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
| 712 |
|
|
WRITE_RCR:
|
| 713 |
|
|
begin
|
| 714 |
|
|
state <= WRITE_RCR_WAIT;
|
| 715 |
|
|
iram_cre <= 1'b1;
|
| 716 |
|
|
iram_ce <= 1'b0;
|
| 717 |
|
|
iram_we <= 1'b0;
|
| 718 |
|
|
iram_a <= RCRReg;
|
| 719 |
|
|
cnt <= tWC;
|
| 720 |
|
|
end
|
| 721 |
|
|
WRITE_RCR_WAIT:
|
| 722 |
|
|
if (cnt_done) begin
|
| 723 |
|
|
state <= WRITE_BCR;
|
| 724 |
|
|
iram_cre <= 1'b0;
|
| 725 |
|
|
iram_ce <= 1'b1;
|
| 726 |
|
|
iram_we <= 1'b1;
|
| 727 |
|
|
end
|
| 728 |
|
|
WRITE_BCR:
|
| 729 |
|
|
begin
|
| 730 |
|
|
state <= WRITE_BCR_WAIT;
|
| 731 |
|
|
iram_cre <= 1'b1;
|
| 732 |
|
|
iram_ce <= 1'b0;
|
| 733 |
|
|
iram_we <= 1'b0;
|
| 734 |
|
|
iram_a <= BCRReg;
|
| 735 |
|
|
cnt <= tWC;
|
| 736 |
|
|
end
|
| 737 |
|
|
WRITE_BCR_WAIT:
|
| 738 |
|
|
if (cnt_done) begin
|
| 739 |
|
|
state <= IDLE; //RANDOMIZE;
|
| 740 |
|
|
iram_cre <= 1'b0;
|
| 741 |
|
|
iram_ce <= 1'b1;
|
| 742 |
|
|
iram_we <= 1'b1;
|
| 743 |
|
|
iram_a <= 23'd0;
|
| 744 |
|
|
end
|
| 745 |
|
|
default:
|
| 746 |
|
|
state <= IDLE;
|
| 747 |
|
|
endcase
|
| 748 |
|
|
end
|
| 749 |
|
|
|
| 750 |
|
|
endmodule
|
| 751 |
|
|
|
