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robfinch |
// ============================================================================
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// 2011 Robert Finch
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// robfinch@<remove>opencores.ca
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//
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// rtfRandom.v
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// Random number generator.
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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// Reg no.
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// 0 random output bits [31:16]
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// 1 random output bits [15: 0]
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// 2 not used
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// 3 not used
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// 4 m_z seed setting bits [31:16]
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// 5 m_z seed setting bits [15 :0]
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// 6 m_w seed setting bits [31:16]
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// 7 m_w seed setting bits [15 :0]
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//
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// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// |WISHBONE Datasheet
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// |WISHBONE SoC Architecture Specification, Revision B.3
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// |
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// |Description: Specifications:
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// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// |General Description: random number generator
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// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// |Supported Cycles: SLAVE,READ/WRITE
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// | SLAVE,BLOCK READ/WRITE
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// | SLAVE,RMW
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// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// |Data port, size: 16 bit
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// |Data port, granularity: 16 bit
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// |Data port, maximum operand size: 16 bit
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// |Data transfer ordering: Undefined
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// |Data transfer sequencing: Undefined
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// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// |Clock frequency constraints: none
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// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// |Supported signal list and Signal Name WISHBONE equiv.
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// |cross reference to equivalent ack_o ACK_O
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// |WISHBONE signals adr_i[43:0] ADR_I()
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// | clk_i CLK_I
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// | rst_i RST_I()
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// | dat_i(15:0) DAT_I()
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// | dat_o(15:0) DAT_O()
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// | cyc_i CYC_I
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// | stb_i STB_I
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// | we_i WE_I
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// |
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// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// |Special requirements:
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// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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//
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// ============================================================================
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//
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// Uses George Marsaglia's multiply method
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//
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// m_w = <choose-initializer>; /* must not be zero */
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// m_z = <choose-initializer>; /* must not be zero */
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//
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// uint get_random()
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// {
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// m_z = 36969 * (m_z & 65535) + (m_z >> 16);
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// m_w = 18000 * (m_w & 65535) + (m_w >> 16);
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// return (m_z << 16) + m_w; /* 32-bit result */
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// }
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//
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module rtfRandom(rst_i, clk_i, cyc_i, stb_i, ack_o, we_i, adr_i, dat_i, dat_o, vol_o);
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input rst_i;
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input clk_i;
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input cyc_i;
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input stb_i;
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output ack_o;
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input we_i;
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input [43:0] adr_i;
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input [15:0] dat_i;
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output [15:0] dat_o;
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reg [15:0] dat_o;
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output vol_o; // outputting a vclatile register
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wire cs = cyc_i && stb_i && (adr_i[43:4]==40'hFFF_FFDC_0C0);
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assign ack_o = cs;
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assign vol_o = cs && !we_i && (adr_i[3:1]==3'd0 || adr_i[3:1]==3'd1);
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reg [31:0] m_z;
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reg [31:0] m_w;
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reg [31:0] next_m_z;
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reg [31:0] next_m_w;
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reg [31:0] out;
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always @(m_z or m_w)
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begin
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next_m_z <= (18'h36969 * m_z[15:0]) + m_z[31:16];
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next_m_w <= (18'h18000 * m_w[15:0]) + m_w[31:16];
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end
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// Register read path
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//
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always @(cs or adr_i or out or m_z or m_w)
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if (cs)
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case(adr_i[3:1])
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3'd0: dat_o <= out[31:16];
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3'd1: dat_o <= out[15: 0];
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// Uncomment these for register read-back
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// 3'd4: dat_o <= m_z[31:16];
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// 3'd5: dat_o <= m_z[15: 0];
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// 3'd6: dat_o <= m_w[31:16];
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// 3'd7: dat_o <= m_w[15: 0];
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endcase
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else
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dat_o <= 16'h0000;
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// Register write path
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//
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always @(posedge clk_i)
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if (rst_i) begin
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m_z <= 32'h01234567; // These must be non-zero
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m_w <= 32'h88888888;
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end
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else begin
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if (cs) begin
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if (we_i)
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case(adr_i[3:1])
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3'd4: m_z[31:16] <= dat_i;
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3'd5: m_z[15: 0] <= dat_i;
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3'd6: m_w[31:16] <= dat_i;
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3'd7: m_w[15: 0] <= dat_i;
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endcase
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// cycle the generator on a read
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else begin
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m_z <= next_m_z;
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m_w <= next_m_w;
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out <= {m_z[15:0],16'd0} + m_w;
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end
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end
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end
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endmodule
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