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robfinch |
/* ============================================================================
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2011 Robert Finch
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robfinch@<remove>sympatico.ca
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rtfSimpleUartTx.v
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This source code is available for evaluation and validation purposes
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only. This copyright statement and disclaimer must remain present in
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the file.
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NO WARRANTY.
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THIS Work, IS PROVIDEDED "AS IS" WITH NO WARRANTIES OF ANY KIND, WHETHER
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EXPRESS OR IMPLIED. The user must assume the entire risk of using the
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Work.
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IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
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INCIDENTAL, CONSEQUENTIAL, OR PUNITIVE DAMAGES WHATSOEVER RELATING TO
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THE USE OF THIS WORK, OR YOUR RELATIONSHIP WITH THE AUTHOR.
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IN ADDITION, IN NO EVENT DOES THE AUTHOR AUTHORIZE YOU TO USE THE WORK
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IN APPLICATIONS OR SYSTEMS WHERE THE WORK'S FAILURE TO PERFORM CAN
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REASONABLY BE EXPECTED TO RESULT IN A SIGNIFICANT PHYSICAL INJURY, OR IN
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LOSS OF LIFE. ANY SUCH USE BY YOU IS ENTIRELY AT YOUR OWN RISK, AND YOU
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AGREE TO HOLD THE AUTHOR AND CONTRIBUTORS HARMLESS FROM ANY CLAIMS OR
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LOSSES RELATING TO SUCH UNAUTHORIZED USE.
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Simple uart transmitter core.
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Features:
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Fixed format 1 start - 8 data - 1 stop bits
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+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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|WISHBONE Datasheet
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|WISHBONE SoC Architecture Specification, Revision B.3
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|Description: Specifications:
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+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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|General Description: simple serial UART transmitter
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+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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|Supported Cycles: SLAVE,WRITE
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| SLAVE,BLOCK WRITE
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+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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|Data port, size: 8 bit
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|Data port, granularity: 8 bit
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|Data port, maximum operand size: 8 bit
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|Data transfer ordering: Undefined
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|Data transfer sequencing: Undefined
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+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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|Clock frequency constraints: none
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+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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|Supported signal list and Signal Name WISHBONE equiv.
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|cross reference to equivalent ack_o ACK_O
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|WISHBONE signals
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| clk_i CLK_I
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| rst_i RST_I
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| dat_i[7:0] DAT_I()
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| cyc_i CYC_I
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| stb_i STB_I
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| we_i WE_I
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+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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|Special requirements:
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+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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REF: Spartan3 - 4
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30 LUTs / 23 slices / 165MHz
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============================================================================ */
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module rtfSimpleUartTx(
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// WISHBONE SoC bus interface
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input rst_i, // reset
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input clk_i, // clock
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input cyc_i, // cycle valid
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input stb_i, // strobe
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output ack_o, // transfer done
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input we_i, // write transmitter
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input [7:0] dat_i, // data in
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//--------------------
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input cs_i, // chip select
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input baud16x_ce, // baud rate clock enable
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input cts, // clear to send
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output txd, // external serial output
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output reg empty // buffer is empty
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);
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reg [9:0] tx_data; // transmit data working reg (raw)
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reg [7:0] fdo; // data output
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reg [7:0] cnt; // baud clock counter
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reg rd;
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assign ack_o = cyc_i & stb_i & cs_i;
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assign txd = tx_data[0];
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always @(posedge clk_i)
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if (ack_o & we_i) fdo <= dat_i;
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// set full / empty status
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always @(posedge clk_i)
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if (rst_i) empty <= 1;
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else begin
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if (ack_o & we_i) empty <= 0;
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else if (rd) empty <= 1;
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end
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always @(posedge clk_i)
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if (rst_i) begin
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cnt <= 8'h00;
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rd <= 0;
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tx_data <= 10'h3FF;
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end
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else begin
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rd <= 0;
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if (baud16x_ce) begin
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cnt <= cnt + 1;
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// Load next data ?
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if (cnt==8'h9F) begin
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cnt <= 0;
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if (!empty && cts) begin
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tx_data <= {1'b1,fdo,1'b0};
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rd <= 1;
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end
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end
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// Shift the data out. LSB first.
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else if (cnt[3:0]==4'hF)
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tx_data <= {1'b1,tx_data[9:1]};
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end
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end
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endmodule
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