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[/] [rtf68ksys/] [trunk/] [rtl/] [verilog/] [rtfSpriteRam.v] - Blame information for rev 2

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// ============================================================================
//  Sprite RAM
//
//      (C) 2005,2011  Robert Finch
//      robfinch<remove>@opencores.org
//
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//                                                                          
// ============================================================================
 
//`define VENDOR_ANY
`define VENDOR_XILINX
`define SPARTAN3
 
module rtfSpriteRam(
clka, adra, dia, doa, cea, wea, rsta,
clkb, adrb, dib, dob, ceb, web, rstb);
parameter pAw = 10;
parameter pDw = 16;
input clka;
input [pAw:1] adra;
input [pDw:1] dia;
output [pDw:1] doa;
input cea;                              // clock enable a
input wea;
input rsta;
input clkb;
input [pAw:1] adrb;
input [pDw:1] dib;
output [pDw:1] dob;
input ceb;                              // clock enable b
input web;
input rstb;
 
`ifdef VENDOR_XILINX
 
`ifdef SPARTAN3
        // could use an S16_S32
        RAMB16_S18_S18 ram0(
                .CLKA(clka), .ADDRA(adra), .DIA(dia), .DIPA(2'b11), .DOA(doa), .ENA(cea), .WEA(wea), .SSRA(rsta),
                .CLKB(clkb), .ADDRB(adrb), .DIB(dib), .DIPB(2'b11), .DOB(dob), .ENB(ceb), .WEB(web), .SSRB(rstb)  );
`else
        // could use an S8_S16
        RAMB4_S8_S8 ram0(
                .CLKA(clka), .ADDRA(adra), .DIA(dia), .DOA(doa), .ENA(cea), .WEA(wea), .RSTA(rsta),
                .CLKB(clkb), .ADDRB(adrb), .DIB(dib), .DOB(dob), .ENB(ceb), .WEB(web), .RSTB(rstb)  );
`endif
`endif
 
`ifdef VENDOR_ALTERA
`endif
 
`ifdef VENDOR_ANY
 
reg [15:0] mem [(1<<pAw):1];
reg [pAw:1] radra;
reg [pAw:1] radrb;
 
// register read addresses
always @(posedge clka)
        if (cea)
                radra <= adra;
 
always @(posedge clkb)
        if (ceb)
                if (web)
                        mem[adrb] <= dib;
 
assign doa = mem[radra];
 
`endif
 
endmodule

Line No.	Rev	Author	Line
1	2	robfinch	`// ============================================================================`
2			`// Sprite RAM`
3			`//`
4			`// (C) 2005,2011 Robert Finch`
5			`// robfinch<remove>@opencores.org`
6			`//`
7			`//`
8			`// This source file is free software: you can redistribute it and/or modify`
9			`// it under the terms of the GNU Lesser General Public License as published`
10			`// by the Free Software Foundation, either version 3 of the License, or`
11			`// (at your option) any later version.`
12			`//`
13			`// This source file is distributed in the hope that it will be useful,`
14			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
15			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
16			`// GNU General Public License for more details.`
17			`//`
18			`// You should have received a copy of the GNU General Public License`
19			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
20			`//`
21			`// ============================================================================`
22
23			//`define VENDOR_ANY
24			`define VENDOR_XILINX
25			`define SPARTAN3
26
27			`module rtfSpriteRam(`
28			`clka, adra, dia, doa, cea, wea, rsta,`
29			`clkb, adrb, dib, dob, ceb, web, rstb);`
30			`parameter pAw = 10;`
31			`parameter pDw = 16;`
32			`input clka;`
33			`input [pAw:1] adra;`
34			`input [pDw:1] dia;`
35			`output [pDw:1] doa;`
36			`input cea; // clock enable a`
37			`input wea;`
38			`input rsta;`
39			`input clkb;`
40			`input [pAw:1] adrb;`
41			`input [pDw:1] dib;`
42			`output [pDw:1] dob;`
43			`input ceb; // clock enable b`
44			`input web;`
45			`input rstb;`
46
47			`ifdef VENDOR_XILINX
48
49			`ifdef SPARTAN3
50			`// could use an S16_S32`
51			`RAMB16_S18_S18 ram0(`
52			`.CLKA(clka), .ADDRA(adra), .DIA(dia), .DIPA(2'b11), .DOA(doa), .ENA(cea), .WEA(wea), .SSRA(rsta),`
53			`.CLKB(clkb), .ADDRB(adrb), .DIB(dib), .DIPB(2'b11), .DOB(dob), .ENB(ceb), .WEB(web), .SSRB(rstb) );`
54			`else
55			`// could use an S8_S16`
56			`RAMB4_S8_S8 ram0(`
57			`.CLKA(clka), .ADDRA(adra), .DIA(dia), .DOA(doa), .ENA(cea), .WEA(wea), .RSTA(rsta),`
58			`.CLKB(clkb), .ADDRB(adrb), .DIB(dib), .DOB(dob), .ENB(ceb), .WEB(web), .RSTB(rstb) );`
59			`endif
60			`endif
61
62			`ifdef VENDOR_ALTERA
63			`endif
64
65			`ifdef VENDOR_ANY
66
67			`reg [15:0] mem [(1<<pAw):1];`
68			`reg [pAw:1] radra;`
69			`reg [pAw:1] radrb;`
70
71			`// register read addresses`
72			`always @(posedge clka)`
73			`if (cea)`
74			`radra <= adra;`
75
76			`always @(posedge clkb)`
77			`if (ceb)`
78			`if (web)`
79			`mem[adrb] <= dib;`
80
81			`assign doa = mem[radra];`
82
83			`endif
84
85			`endmodule`

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[/] [rtf68ksys/] [trunk/] [rtl/] [verilog/] [rtfSpriteRam.v] - Blame information for rev 2