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robfinch |
// ============================================================================
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// (C) 2005-2011 Robert Finch
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// All Rights Reserved.
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//
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// seven_seg.v
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// Seven segment display driver.
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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// Webpack 9.2i xc3s1200e 4fg320
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// 32 slices / 62 LUTs / 208.160 MHz
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// 27 ff's / 1 DCM
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//
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// 500us on per digit
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// 10us interdigit blanking
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//=============================================================================
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module seven_seg(rst, clk, dp, val, ssLedAnode, ssLedSeg);
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parameter pClkFreq=25000000;
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parameter pTermCnt=pClkFreq/250000;
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input rst; // reset
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input clk; // clock
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input [3:0] dp;
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input [15:0] val;
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output [3:0] ssLedAnode;
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output [7:0] ssLedSeg;
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reg [3:0] ssLedAnode;
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reg [7:0] ssLedSeg;
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// Generate 250kHz clock from input
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wire [ 9:0] q1;
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wire [11:0] q2;
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down_counter #(10) u1 (rst, clk, 1'b1, z, pTermCnt, q1, z);
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counter #(12) u2 (rst, clk, z, 1'b0, 12'h000, q2);
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reg [4:0] nyb;
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wire [2:0] dig_ndx = q2[11:9];
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wire dig_en = q2[8:1]!=8'hFF;
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always @(dig_ndx or dig_en)
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if (dig_en)
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case (dig_ndx)
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3'd0: ssLedAnode = 4'hE;
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3'd1: ssLedAnode = 4'hD;
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3'd2: ssLedAnode = 4'hB;
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3'd3: ssLedAnode = 4'h7;
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default: ssLedAnode = 4'hF;
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endcase
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else
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ssLedAnode = 4'hF;
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always @(dig_ndx or dp or val)
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case (dig_ndx)
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3'd0: nyb = {dp[0],val[ 3: 0]};
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3'd1: nyb = {dp[1],val[ 7: 4]};
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3'd2: nyb = {dp[2],val[11: 8]};
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3'd3: nyb = {dp[3],val[15:12]};
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default: nyb = 5'd0;
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endcase
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always @(dig_en or nyb)
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if (dig_en) begin
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case (nyb[3:0])
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4'h0: ssLedSeg <= 8'b11000000;
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4'h1: ssLedSeg <= 8'b11111001;
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4'h2: ssLedSeg <= 8'b10100100;
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4'h3: ssLedSeg <= 8'b10110000;
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4'h4: ssLedSeg <= 8'b10011001;
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4'h5: ssLedSeg <= 8'b10010010;
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4'h6: ssLedSeg <= 8'b10000010;
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4'h7: ssLedSeg <= 8'b11111000;
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4'h8: ssLedSeg <= 8'b10000000;
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4'h9: ssLedSeg <= 8'b10011000;
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4'hA: ssLedSeg <= 8'b10001000;
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4'hB: ssLedSeg <= 8'b10000011;
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4'hC: ssLedSeg <= 8'b11000110;
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4'hD: ssLedSeg <= 8'b10100001;
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4'hE: ssLedSeg <= 8'b10000110;
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4'hF: ssLedSeg <= 8'b10001110;
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endcase
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ssLedSeg[7] <= !nyb[4];
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end
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else
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ssLedSeg <= 8'b11111111;
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endmodule
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