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robfinch |
// ============================================================================
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// 2008,2011 Robert Finch
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// robfinch@<remove>sympatico.ca
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//
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// syncRam4kx9_1rw1r.v
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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// ============================================================================
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//
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`define SYNTHESIS
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`define VENDOR_XILINX
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`define SPARTAN3
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module syncRam4kx9_1rw1r(
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input wrst,
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input wclk,
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input wce,
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input we,
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input [11:0] wadr,
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input [8:0] i,
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output [8:0] wo,
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input rrst,
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input rclk,
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input rce,
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input [11:0] radr,
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output [8:0] o
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);
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`ifdef SYNTHESIS
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`ifdef VENDOR_XILINX
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`ifdef SPARTAN3
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wire [8:0] o0;
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wire [8:0] o1;
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wire [8:0] wo0;
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wire [8:0] wo1;
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wire rrst0 = radr[11];
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wire rrst1 = ~radr[11];
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wire wrst0 = wadr[11];
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wire wrst1 = ~wadr[11];
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wire we0 = we & ~wadr[11];
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wire we1 = we & wadr[11];
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RAMB16_S9_S9 ram0(
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.CLKA(wclk), .ADDRA(wadr), .DIA(i[7:0]), .DIPA(i[8]), .DOA(wo0[7:0]), .DOPA(wo0[8]), .ENA(wce), .WEA(we0), .SSRA(wrst0),
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.CLKB(rclk), .ADDRB(radr), .DIB(8'hFF), .DIPB(1'b1), .DOB(o0[7:0]), .DOPB(o0[8]), .ENB(rce), .WEB(1'b0), .SSRB(rrst0) );
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RAMB16_S9_S9 ram1(
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.CLKA(wclk), .ADDRA(wadr), .DIA(i[7:0]), .DIPA(i[8]), .DOA(wo1[7:0]), .DOPA(wo1[8]), .ENA(wce), .WEA(we1), .SSRA(wrst1),
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.CLKB(rclk), .ADDRB(radr), .DIB(8'hFF), .DIPB(1'b1), .DOB(o1[7:0]), .DOPB(o1[8]), .ENB(rce), .WEB(1'b0), .SSRB(rrst1) );
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assign o = o0|o1;
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assign wo = wo0|wo1;
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`endif
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`ifdef SPARTAN2
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RAMB4_S1_S1 ram0(
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.CLKA(wclk), .ADDRA(wadr), .DIA(i[0]), .DOA(wo[0]), .ENA(wce), .WEA(we), .RSTA(wrst),
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.CLKB(rclk), .ADDRB(radr), .DIB(1'b1), .DOB(o[0]), .ENB(rce), .WEB(1'b0), .RSTB(rrst) );
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RAMB4_S1_S1 ram1(
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.CLKA(wclk), .ADDRA(wadr), .DIA(i[1]), .DOA(wo[1]), .ENA(wce), .WEA(we), .RSTA(wrst),
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.CLKB(rclk), .ADDRB(radr), .DIB(1'b1), .DOB(o[1]), .ENB(rce), .WEB(1'b0), .RSTB(rrst) );
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RAMB4_S1_S1 ram2(
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.CLKA(wclk), .ADDRA(wadr), .DIA(i[2]), .DOA(wo[2]), .ENA(wce), .WEA(we), .RSTA(wrst),
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.CLKB(rclk), .ADDRB(radr), .DIB(1'b1), .DOB(o[2]), .ENB(rce), .WEB(1'b0), .RSTB(rrst) );
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RAMB4_S1_S1 ram3(
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.CLKA(wclk), .ADDRA(wadr), .DIA(i[3]), .DOA(wo[3]), .ENA(wce), .WEA(we), .RSTA(wrst),
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.CLKB(rclk), .ADDRB(radr), .DIB(1'b1), .DOB(o[3]), .ENB(rce), .WEB(1'b0), .RSTB(rrst) );
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RAMB4_S1_S1 ram4(
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.CLKA(wclk), .ADDRA(wadr), .DIA(i[4]), .DOA(wo[4]), .ENA(wce), .WEA(we), .RSTA(wrst),
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.CLKB(rclk), .ADDRB(radr), .DIB(1'b1), .DOB(o[4]), .ENB(rce), .WEB(1'b0), .RSTB(rrst) );
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RAMB4_S1_S1 ram5(
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.CLKA(wclk), .ADDRA(wadr), .DIA(i[5]), .DOA(wo[5]), .ENA(wce), .WEA(we), .RSTA(wrst),
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.CLKB(rclk), .ADDRB(radr), .DIB(1'b1), .DOB(o[5]), .ENB(rce), .WEB(1'b0), .RSTB(rrst) );
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RAMB4_S1_S1 ram6(
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.CLKA(wclk), .ADDRA(wadr), .DIA(i[6]), .DOA(wo[6]), .ENA(wce), .WEA(we), .RSTA(wrst),
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.CLKB(rclk), .ADDRB(radr), .DIB(1'b1), .DOB(o[6]), .ENB(rce), .WEB(1'b0), .RSTB(rrst) );
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RAMB4_S1_S1 ram7(
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.CLKA(wclk), .ADDRA(wadr), .DIA(i[7]), .DOA(wo[7]), .ENA(wce), .WEA(we), .RSTA(wrst),
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.CLKB(rclk), .ADDRB(radr), .DIB(1'b1), .DOB(o[7]), .ENB(rce), .WEB(1'b0), .RSTB(rrst) );
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RAMB4_S1_S1 ram8(
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.CLKA(wclk), .ADDRA(wadr), .DIA(i[8]), .DOA(wo[8]), .ENA(wce), .WEA(we), .RSTA(wrst),
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.CLKB(rclk), .ADDRB(radr), .DIB(1'b1), .DOB(o[8]), .ENB(rce), .WEB(1'b0), .RSTB(rrst) );
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`endif
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`endif
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`ifdef VENDOR_ALTERA
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reg [8:0] mem [4095:0];
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reg [10:0] rradr;
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reg [10:0] rwadr;
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// register read addresses
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always @(posedge rclk)
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if (rce) rradr <= radr;
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assign o = mem[rradr];
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// write side
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always @(posedge wclk)
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if (wce) rwadr <= wadr;
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always @(posedge wclk)
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if (wce) mem[wadr] <= i;
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assign wo = mem[rwadr];
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`endif
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`else
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reg [8:0] mem [4095:0];
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reg [10:0] rradr;
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reg [10:0] rwadr;
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// register read addresses
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always @(posedge rclk)
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if (rce) rradr <= radr;
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assign o = mem[rradr];
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// write side
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always @(posedge wclk)
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if (wce) rwadr <= wadr;
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always @(posedge wclk)
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if (wce) mem[wadr] <= i;
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assign wo = mem[rwadr];
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`endif
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endmodule
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