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[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [CMPSB.v] - Blame information for rev 3

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//=============================================================================
//  CMPSB
//
//
//  2009-2012 Robert Finch
//  Stratford
//  robfinch<remove>@opencores.org
//
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//
//
//=============================================================================
//
CMPSB:
`include "check_for_ints.v"
        else begin
                cyc_type <= `CT_RDMEM;
                lock_o <= 1'b0;
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                we_o  <= 1'b0;
                adr_o <= {seg_reg,`SEG_SHIFT} + si;
                state <= CMPSB1;
        end
CMPSB1:
        if (ack_i) begin
                state <= CMPSB2;
                `TERMINATE_CYCLE
                lock_o <= 1'b0;
                a[ 7:0] <= dat_i[7:0];
                a[15:8] <= {8{dat_i[7]}};
        end
CMPSB2:
        begin
                state <= CMPSB3;
                cyc_type <= `CT_RDMEM;
                lock_o <= 1'b0;
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                we_o  <= 1'b0;
                adr_o <= esdi;
        end
CMPSB3:
        if (ack_i) begin
                state <= CMPSB4;
                `TERMINATE_CYCLE
                lock_o <= 1'b0;
                b[ 7:0] <= dat_i[7:0];
                b[15:8] <= {8{dat_i[7]}};
        end
CMPSB4:
        begin
                pf <= pres;
                zf <= reszb;
                sf <= resnb;
                af <= carry   (1'b1,a[3],b[3],alu_o[3]);
                cf <= carry   (1'b1,a[7],b[7],alu_o[7]);
                vf <= overflow(1'b1,a[7],b[7],alu_o[7]);
                if (df) begin
                        si <= si_dec;
                        di <= di_dec;
                end
                else begin
                        si <= si_inc;
                        di <= di_inc;
                end
                if ((repz & !cxz & zf) | (repnz & !cxz & !zf)) begin
                        cx <= cx_dec;
                        state <= CMPSB;
                end
                else
                        state <= IFETCH;
        end
 

Line No.	Rev	Author	Line
1	2	robfinch	`//=============================================================================`
2			`// CMPSB`
3			`//`
4			`//`
5			`// 2009-2012 Robert Finch`
6			`// Stratford`
7			`// robfinch<remove>@opencores.org`
8			`//`
9			`//`
10			`// This source file is free software: you can redistribute it and/or modify`
11			`// it under the terms of the GNU Lesser General Public License as published`
12			`// by the Free Software Foundation, either version 3 of the License, or`
13			`// (at your option) any later version.`
14			`//`
15			`// This source file is distributed in the hope that it will be useful,`
16			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
17			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
18			`// GNU General Public License for more details.`
19			`//`
20			`// You should have received a copy of the GNU General Public License`
21			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
22			`//`
23			`//`
24			`//=============================================================================`
25			`//`
26			`CMPSB:`
27			`include "check_for_ints.v"
28			`else begin`
29			cyc_type <= `CT_RDMEM;
30			`lock_o <= 1'b0;`
31			`cyc_o <= 1'b1;`
32			`stb_o <= 1'b1;`
33			`we_o <= 1'b0;`
34			adr_o <= {seg_reg,`SEG_SHIFT} + si;
35			`state <= CMPSB1;`
36			`end`
37			`CMPSB1:`
38			`if (ack_i) begin`
39			`state <= CMPSB2;`
40			`TERMINATE_CYCLE
41			`lock_o <= 1'b0;`
42			`a[ 7:0] <= dat_i[7:0];`
43			`a[15:8] <= {8{dat_i[7]}};`
44			`end`
45			`CMPSB2:`
46			`begin`
47			`state <= CMPSB3;`
48			cyc_type <= `CT_RDMEM;
49			`lock_o <= 1'b0;`
50			`cyc_o <= 1'b1;`
51			`stb_o <= 1'b1;`
52			`we_o <= 1'b0;`
53			`adr_o <= esdi;`
54			`end`
55			`CMPSB3:`
56			`if (ack_i) begin`
57			`state <= CMPSB4;`
58			`TERMINATE_CYCLE
59			`lock_o <= 1'b0;`
60			`b[ 7:0] <= dat_i[7:0];`
61			`b[15:8] <= {8{dat_i[7]}};`
62			`end`
63			`CMPSB4:`
64			`begin`
65			`pf <= pres;`
66			`zf <= reszb;`
67			`sf <= resnb;`
68			`af <= carry (1'b1,a[3],b[3],alu_o[3]);`
69			`cf <= carry (1'b1,a[7],b[7],alu_o[7]);`
70			`vf <= overflow(1'b1,a[7],b[7],alu_o[7]);`
71			`if (df) begin`
72			`si <= si_dec;`
73			`di <= di_dec;`
74			`end`
75			`else begin`
76			`si <= si_inc;`
77			`di <= di_inc;`
78			`end`
79			`if ((repz & !cxz & zf) \| (repnz & !cxz & !zf)) begin`
80			`cx <= cx_dec;`
81			`state <= CMPSB;`
82			`end`
83			`else`
84			`state <= IFETCH;`
85			`end`
86

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[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [CMPSB.v] - Blame information for rev 3