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[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [CMPSW.v] - Blame information for rev 4

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//=============================================================================
//  CMPSW
//
//
//  2009,2010 Robert Finch
//  Stratford
//  robfinch<remove>@opencores.org
//
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//
//
//=============================================================================
//
CMPSW:
`include "check_for_ints.v"
        else begin
                cyc_type <= `CT_RDMEM;
                lock_o <= 1'b0;
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                we_o  <= 1'b0;
                adr_o <= {seg_reg,4'b0} + si;
                state <= CMPSW1;
        end
CMPSW1:
        if (ack_i) begin
                cyc_type <= `CT_PASSIVE;
                stb_o <= 1'b0;
                if (df) begin
                        si <= si_dec;
                        a[15:8] <= dat_i;
                end
                else begin
                        si <= si_inc;
                        a[ 7:0] <= dat_i;
                end
                state <= CMPSW2;
        end
CMPSW2:
        if (!stb_o) begin
                cyc_type <= `CT_RDMEM;
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                we_o  <= 1'b0;
                adr_o <= {seg_reg,4'b0} + si;
        end
        else if (ack_i) begin
                cyc_type <= `CT_PASSIVE;
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                if (df) begin
                        si <= si_dec;
                        a[7:0] <= dat_i;
                end
                else begin
                        si <= si_inc;
                        a[15:8] <= dat_i;
                end
                state <= CMPSW3;
        end
CMPSW3:
        if (!cyc_o) begin
                cyc_type <= `CT_RDMEM;
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                adr_o <= esdi;
        end
        else if (ack_i) begin
                cyc_type <= `CT_PASSIVE;
                stb_o <= 1'b0;
                if (df) begin
                        di <= di_dec;
                        b[15:8] <= dat_i;
                end
                else begin
                        di <= di_inc;
                        b[ 7:0] <= dat_i;
                end
                state <= CMPSW4;
        end
CMPSW4:
        if (!stb_o) begin
                cyc_type <= `CT_RDMEM;
                lock_o <= 1'b0;
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                we_o  <= 1'b0;
                adr_o <= esdi;
        end
        else if (ack_i) begin
                cyc_type <= `CT_PASSIVE;
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                if (df) begin
                        di <= di_dec;
                        b[7:0] <= dat_i;
                end
                else begin
                        di <= di_inc;
                        b[15:8] <= dat_i;
                end
                state <= CMPSW5;
        end
CMPSW5:
        begin
                pf <= pres;
                zf <= reszw;
                sf <= resnw;
                af <= carry   (1'b1,a[3],b[3],alu_o[3]);
                cf <= carry   (1'b1,a[15],b[15],alu_o[15]);
                vf <= overflow(1'b1,a[15],b[15],alu_o[15]);
                if ((repz & !cxz & zf) | (repnz & !cxz & !zf)) begin
                        cx <= cx_dec;
                        state <= CMPSW;
                end
                else
                        state <= IFETCH;
        end
 

Line No.	Rev	Author	Line
1	2	robfinch	`//=============================================================================`
2			`// CMPSW`
3			`//`
4			`//`
5			`// 2009,2010 Robert Finch`
6			`// Stratford`
7			`// robfinch<remove>@opencores.org`
8			`//`
9			`//`
10			`// This source file is free software: you can redistribute it and/or modify`
11			`// it under the terms of the GNU Lesser General Public License as published`
12			`// by the Free Software Foundation, either version 3 of the License, or`
13			`// (at your option) any later version.`
14			`//`
15			`// This source file is distributed in the hope that it will be useful,`
16			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
17			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
18			`// GNU General Public License for more details.`
19			`//`
20			`// You should have received a copy of the GNU General Public License`
21			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
22			`//`
23			`//`
24			`//=============================================================================`
25			`//`
26			`CMPSW:`
27			`include "check_for_ints.v"
28			`else begin`
29			cyc_type <= `CT_RDMEM;
30			`lock_o <= 1'b0;`
31			`cyc_o <= 1'b1;`
32			`stb_o <= 1'b1;`
33			`we_o <= 1'b0;`
34			`adr_o <= {seg_reg,4'b0} + si;`
35			`state <= CMPSW1;`
36			`end`
37			`CMPSW1:`
38			`if (ack_i) begin`
39			cyc_type <= `CT_PASSIVE;
40			`stb_o <= 1'b0;`
41			`if (df) begin`
42			`si <= si_dec;`
43			`a[15:8] <= dat_i;`
44			`end`
45			`else begin`
46			`si <= si_inc;`
47			`a[ 7:0] <= dat_i;`
48			`end`
49			`state <= CMPSW2;`
50			`end`
51			`CMPSW2:`
52			`if (!stb_o) begin`
53			cyc_type <= `CT_RDMEM;
54			`cyc_o <= 1'b1;`
55			`stb_o <= 1'b1;`
56			`we_o <= 1'b0;`
57			`adr_o <= {seg_reg,4'b0} + si;`
58			`end`
59			`else if (ack_i) begin`
60			cyc_type <= `CT_PASSIVE;
61			`cyc_o <= 1'b0;`
62			`stb_o <= 1'b0;`
63			`if (df) begin`
64			`si <= si_dec;`
65			`a[7:0] <= dat_i;`
66			`end`
67			`else begin`
68			`si <= si_inc;`
69			`a[15:8] <= dat_i;`
70			`end`
71			`state <= CMPSW3;`
72			`end`
73			`CMPSW3:`
74			`if (!cyc_o) begin`
75			cyc_type <= `CT_RDMEM;
76			`cyc_o <= 1'b1;`
77			`stb_o <= 1'b1;`
78			`adr_o <= esdi;`
79			`end`
80			`else if (ack_i) begin`
81			cyc_type <= `CT_PASSIVE;
82			`stb_o <= 1'b0;`
83			`if (df) begin`
84			`di <= di_dec;`
85			`b[15:8] <= dat_i;`
86			`end`
87			`else begin`
88			`di <= di_inc;`
89			`b[ 7:0] <= dat_i;`
90			`end`
91			`state <= CMPSW4;`
92			`end`
93			`CMPSW4:`
94			`if (!stb_o) begin`
95			cyc_type <= `CT_RDMEM;
96			`lock_o <= 1'b0;`
97			`cyc_o <= 1'b1;`
98			`stb_o <= 1'b1;`
99			`we_o <= 1'b0;`
100			`adr_o <= esdi;`
101			`end`
102			`else if (ack_i) begin`
103			cyc_type <= `CT_PASSIVE;
104			`cyc_o <= 1'b0;`
105			`stb_o <= 1'b0;`
106			`if (df) begin`
107			`di <= di_dec;`
108			`b[7:0] <= dat_i;`
109			`end`
110			`else begin`
111			`di <= di_inc;`
112			`b[15:8] <= dat_i;`
113			`end`
114			`state <= CMPSW5;`
115			`end`
116			`CMPSW5:`
117			`begin`
118			`pf <= pres;`
119			`zf <= reszw;`
120			`sf <= resnw;`
121			`af <= carry (1'b1,a[3],b[3],alu_o[3]);`
122			`cf <= carry (1'b1,a[15],b[15],alu_o[15]);`
123			`vf <= overflow(1'b1,a[15],b[15],alu_o[15]);`
124			`if ((repz & !cxz & zf) \| (repnz & !cxz & !zf)) begin`
125			`cx <= cx_dec;`
126			`state <= CMPSW;`
127			`end`
128			`else`
129			`state <= IFETCH;`
130			`end`
131

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[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [CMPSW.v] - Blame information for rev 4