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[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [DECODER2.v] - Blame information for rev 3

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Line No. Rev Author Line
1 2 robfinch
// ============================================================================
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//  DECODER2.v
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//  - Extended opcode decoder
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//
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//
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//  2009-2012  Robert Finch
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//  robfinch[remove]@opencores.org
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//  Stratford
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//
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//  
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// This source file is free software: you can redistribute it and/or modify 
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// it under the terms of the GNU Lesser General Public License as published 
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// by the Free Software Foundation, either version 3 of the License, or     
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// (at your option) any later version.                                      
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//                                                                          
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// This source file is distributed in the hope that it will be useful,      
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// but WITHOUT ANY WARRANTY; without even the implied warranty of           
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
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// GNU General Public License for more details.                             
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//                                                                          
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// You should have received a copy of the GNU General Public License        
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
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//
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//
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//  Verilog 
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//
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// ============================================================================
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//
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//
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DECODER2:
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        begin
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                state <= IFETCH;
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                case(ir)
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                `MORE1:
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                        casex(ir2)
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                        `AAM:
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                                begin
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                                        wrregs <= 1'b1;
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                                        w <= 1'b1;
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                                        rrr <= 3'd0;
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                                        res <= alu_o;
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                                        sf <= 1'b0;
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                                        zf <= reszb;
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                                        pf <= pres;
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                                end
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                        default:        ;
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                        endcase
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                `MORE2:
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                        casex(ir2)
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                        `AAD:
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                                begin
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                                        wrregs <= 1'b1;
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                                        w <= 1'b1;
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                                        rrr <= 3'd0;
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                                        res <= alu_o;
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                                        sf <= 1'b0;
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                                        zf <= reszw;
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                                        pf <= pres;
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                                end
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                        default:        ;
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                        endcase
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                `EXTOP:
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                        casex(ir2)
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                        `LxDT:
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                                begin
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                                        w <= 1'b1;
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                                        `INITIATE_CODE_READ
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                                        state <= EACALC;                // override state transition
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                                end
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                        default:        ;
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                        endcase
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                default:        ;
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                endcase
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        end
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