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[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [DECODER2.v] - Blame information for rev 3

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// ============================================================================
//  DECODER2.v
//  - Extended opcode decoder
//
//
//  2009-2012  Robert Finch
//  robfinch[remove]@opencores.org
//  Stratford
//
//  
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//
//
//  Verilog 
//
// ============================================================================
//
//
DECODER2:
        begin
                state <= IFETCH;
                case(ir)
                `MORE1:
                        casex(ir2)
                        `AAM:
                                begin
                                        wrregs <= 1'b1;
                                        w <= 1'b1;
                                        rrr <= 3'd0;
                                        res <= alu_o;
                                        sf <= 1'b0;
                                        zf <= reszb;
                                        pf <= pres;
                                end
                        default:        ;
                        endcase
                `MORE2:
                        casex(ir2)
                        `AAD:
                                begin
                                        wrregs <= 1'b1;
                                        w <= 1'b1;
                                        rrr <= 3'd0;
                                        res <= alu_o;
                                        sf <= 1'b0;
                                        zf <= reszw;
                                        pf <= pres;
                                end
                        default:        ;
                        endcase
                `EXTOP:
                        casex(ir2)
                        `LxDT:
                                begin
                                        w <= 1'b1;
                                        `INITIATE_CODE_READ
                                        state <= EACALC;                // override state transition
                                end
                        default:        ;
                        endcase
                default:        ;
                endcase
        end
 

Line No.	Rev	Author	Line
1	2	robfinch	`// ============================================================================`
2			`// DECODER2.v`
3			`// - Extended opcode decoder`
4			`//`
5			`//`
6			`// 2009-2012 Robert Finch`
7			`// robfinch[remove]@opencores.org`
8			`// Stratford`
9			`//`
10			`//`
11			`// This source file is free software: you can redistribute it and/or modify`
12			`// it under the terms of the GNU Lesser General Public License as published`
13			`// by the Free Software Foundation, either version 3 of the License, or`
14			`// (at your option) any later version.`
15			`//`
16			`// This source file is distributed in the hope that it will be useful,`
17			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
18			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
19			`// GNU General Public License for more details.`
20			`//`
21			`// You should have received a copy of the GNU General Public License`
22			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
23			`//`
24			`//`
25			`// Verilog`
26			`//`
27			`// ============================================================================`
28			`//`
29			`//`
30			`DECODER2:`
31			`begin`
32			`state <= IFETCH;`
33			`case(ir)`
34			`MORE1:
35			`casex(ir2)`
36			`AAM:
37			`begin`
38			`wrregs <= 1'b1;`
39			`w <= 1'b1;`
40			`rrr <= 3'd0;`
41			`res <= alu_o;`
42			`sf <= 1'b0;`
43			`zf <= reszb;`
44			`pf <= pres;`
45			`end`
46			`default: ;`
47			`endcase`
48			`MORE2:
49			`casex(ir2)`
50			`AAD:
51			`begin`
52			`wrregs <= 1'b1;`
53			`w <= 1'b1;`
54			`rrr <= 3'd0;`
55			`res <= alu_o;`
56			`sf <= 1'b0;`
57			`zf <= reszw;`
58			`pf <= pres;`
59			`end`
60			`default: ;`
61			`endcase`
62			`EXTOP:
63			`casex(ir2)`
64			`LxDT:
65			`begin`
66			`w <= 1'b1;`
67			`INITIATE_CODE_READ
68			`state <= EACALC; // override state transition`
69			`end`
70			`default: ;`
71			`endcase`
72			`default: ;`
73			`endcase`
74			`end`
75

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[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [DECODER2.v] - Blame information for rev 3