OpenCores
URL https://opencores.org/ocsvn/rtf8088/rtf8088/trunk

Subversion Repositories rtf8088

[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [EVALUATE_BRANCH.v] - Blame information for rev 4

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 robfinch
// ============================================================================
2
//  EVALUATE_BRANCH.v
3
//  Evaluate branch condition
4
//
5
//
6
//  (C) 2009,2010  Robert Finch
7
//  Stratford
8
//  robfinch[remove]@opencores.ca
9
//
10
//  
11
//  This source code is available for evaluation and validation purposes
12
//  only. This copyright statement and disclaimer must remain present in
13
//  the file.
14
//
15
//      NO WARRANTY.
16
//  THIS Work, IS PROVIDEDED "AS IS" WITH NO WARRANTIES OF ANY KIND, WHETHER
17
//  EXPRESS OR IMPLIED. The user must assume the entire risk of using the
18
//  Work.
19
//
20
//  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
21
//  INCIDENTAL, CONSEQUENTIAL, OR PUNITIVE DAMAGES WHATSOEVER RELATING TO
22
//  THE USE OF THIS WORK, OR YOUR RELATIONSHIP WITH THE AUTHOR.
23
//
24
//  IN ADDITION, IN NO EVENT DOES THE AUTHOR AUTHORIZE YOU TO USE THE WORK
25
//  IN APPLICATIONS OR SYSTEMS WHERE THE WORK'S FAILURE TO PERFORM CAN
26
//  REASONABLY BE EXPECTED TO RESULT IN A SIGNIFICANT PHYSICAL INJURY, OR IN
27
//  LOSS OF LIFE. ANY SUCH USE BY YOU IS ENTIRELY AT YOUR OWN RISK, AND YOU
28
//  AGREE TO HOLD THE AUTHOR AND CONTRIBUTORS HARMLESS FROM ANY CLAIMS OR
29
//  LOSSES RELATING TO SUCH UNAUTHORIZED USE.
30
//
31
//
32
//  Verilog 
33
//
34
// ============================================================================
35
//
36
`ifndef JMPS
37
`define JMPS    8'hEB
38
`endif
39
 
40
`ifndef JO
41
`define JO              8'h70
42
`define JNO             8'h71
43
`define JB              8'h72
44
`define JAE             8'h73
45
`define JE              8'h74
46
`define JNE             8'h75
47
`define JBE             8'h76
48
`define JA              8'h77
49
`define JS              8'h78
50
`define JNS             8'h79
51
`define JP              8'h7A
52
`define JNP             8'h7B
53
`define JL              8'h7C
54
`define JNL             8'h7D
55
`define JLE             8'h7E
56
`define JNLE    8'h7F
57
 
58
`define JNA             8'h76
59
`define JNAE    8'h72
60
`define JNB     8'h73
61
`define JNBE    8'h77
62
`define JC      8'h72
63
`define JNC     8'h73
64
`define JG              8'h7F
65
`define JNG             8'h7E
66
`define JGE             8'h7D
67
`define JNGE    8'h7C
68
`define JPE     8'h7A
69
`define JPO     8'h7B
70
 
71
`define LOOPNZ  8'hE0
72
`define LOOPZ   8'hE1
73
`define LOOP    8'hE2
74
`define JCXZ    8'hE3
75
 
76
`endif
77
 
78
module evaluate_branch(ir,cx,zf,cf,sf,vf,pf,take_br);
79
input [7:0] ir;
80
input [15:0] cx;
81
input zf,cf,sf,vf,pf;
82
output take_br;
83
 
84
reg take_br;
85
wire cxo = cx==16'h0001;        // CX is one
86
wire cxz = cx==16'h0000;        // CX is zero
87
 
88
always @(ir or cx or cxz or cxo or zf or cf or sf or vf or pf)
89
        case(ir)
90
        `JMPS:          take_br <= 1'b1;
91
        `JP:            take_br <=  pf;
92
        `JNP:           take_br <= !pf;
93
        `JO:            take_br <=  vf;
94
        `JNO:           take_br <= !vf;
95
        `JE:            take_br <=  zf;
96
        `JNE:           take_br <= !zf;
97
        `JAE:           take_br <= !cf;
98
        `JB:            take_br <=  cf;
99
        `JS:            take_br <=  sf;
100
        `JNS:           take_br <= !sf;
101
        `JBE:           take_br <=  cf | zf;
102
        `JA:            take_br <= !cf & !zf;
103
        `JL:            take_br <= sf ^ vf;
104
        `JNL:           take_br <= !(sf ^ vf);
105
        `JLE:           take_br <= (sf ^ vf) | zf;
106
        `JNLE:          take_br <= !((sf ^ vf) | zf);
107
        `JCXZ:          take_br <= cxz;
108
        `LOOP:          take_br <= !cxo;
109
        `LOOPZ:         take_br <= !cxo && zf;
110
        `LOOPNZ:        take_br <= !cxo && !zf;
111
        default:        take_br <= 1'b0;
112
        endcase
113
 
114
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.