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// ============================================================================
//  (C) 2009,2010,2012  Robert Finch
//  robfinch<remove>@opencores.org
//
//  EXECUTE
//  - execute instruction
//
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//
//
//  Verilog 
//
// ============================================================================
//
EXECUTE:
        begin
                casex(ir)
 
                `EXTOP:
                        casex(ir2)
                        `LxDT: state <= FETCH_DESC;
                        endcase
 
                `DAA:
                        begin
                                state <= IFETCH;
                        end
 
                `ALU_I2R8,`ALU_I2R16,`ADD,`ADD_ALI8,`ADD_AXI16,`ADC,`ADC_ALI8,`ADC_AXI16:
                        begin
                                state <= IFETCH;
                                wrregs <= 1'b1;
                                res <= alu_o;
                                pf <= pres;
                                af <= carry   (1'b0,a[3],b[3],alu_o[3]);
                                cf <= carry   (1'b0,amsb,bmsb,resn);
                                vf <= overflow(1'b0,amsb,bmsb,resn);
                                sf <= resn;
                                zf <= resz;
                        end
 
                `AND,`OR,`XOR,`AND_ALI8,`OR_ALI8,`XOR_ALI8,`AND_AXI16,`OR_AXI16,`XOR_AXI16:
                        begin
                                state <= IFETCH;
                                wrregs <= 1'b1;
                                res <= alu_o;
                                pf <= pres;
                                cf <= 1'b0;
                                vf <= 1'b0;
                                sf <= resn;
                                zf <= resz;
                        end
 
                `TEST:
                        begin
                                state <= IFETCH;
                                res <= alu_o;
                                pf <= pres;
                                cf <= 1'b0;
                                vf <= 1'b0;
                                sf <= resn;
                                zf <= resz;
                        end
 
                `CMP,`CMP_ALI8,`CMP_AXI16:
                        begin
                                state <= IFETCH;
                                pf <= pres;
                                af <= carry   (1'b1,a[3],b[3],alu_o[3]);
                                cf <= carry   (1'b1,amsb,bmsb,resn);
                                vf <= overflow(1'b1,amsb,bmsb,resn);
                                sf <= resn;
                                zf <= resz;
                        end
 
                `SBB,`SUB,`SBB_ALI8,`SUB_ALI8,`SBB_AXI16,`SUB_AXI16:
                        begin
                                wrregs <= 1'b1;
                                state <= IFETCH;
                                res <= alu_o;
                                pf <= pres;
                                af <= carry   (1'b1,a[3],b[3],alu_o[3]);
                                cf <= carry   (1'b1,amsb,bmsb,resn);
                                vf <= overflow(1'b1,amsb,bmsb,resn);
                                sf <= resn;
                                zf <= resz;
                        end
 
                8'hF6,8'hF7:
                        begin
                                state <= IFETCH;
                                res <= alu_o;
                                case(TTT)
                                3'd0:   // TEST
                                        begin
                                                pf <= pres;
                                                cf <= 1'b0;
                                                vf <= 1'b0;
                                                sf <= resn;
                                                zf <= resz;
                                        end
                                3'd2:   // NOT
                                        begin
                                                wrregs <= 1'b1;
                                        end
                                3'd3:   // NEG
                                        begin
                                                pf <= pres;
                                                af <= carry   (1'b1,1'b0,b[3],alu_o[3]);
                                                cf <= carry   (1'b1,1'b0,bmsb,resn);
                                                vf <= overflow(1'b1,1'b0,bmsb,resn);
                                                sf <= resn;
                                                zf <= resz;
                                                wrregs <= 1'b1;
                                        end
                                // Normally only a single register update is required, however with 
                                // multiply word both AX and DX need to be updated. So we bypass the
                                // regular update here.
                                3'd4:
                                        begin
                                                if (w) begin
                                                        ax <= p32[15:0];
                                                        dx <= p32[31:16];
                                                        cf <= p32[31:16]!=16'd0;
                                                        vf <= p32[31:16]!=16'd0;
                                                end
                                                else begin
                                                        ax <= p16;
                                                        cf <= p16[15:8]!=8'd0;
                                                        vf <= p16[15:8]!=8'd0;
                                                end
                                        end
                                3'd5:
                                        begin
                                                if (w) begin
                                                        ax <= wp[15:0];
                                                        dx <= wp[31:16];
                                                        cf <= p32[31:16]!=16'd0;
                                                        vf <= p32[31:16]!=16'd0;
                                                end
                                                else begin
                                                        ax <= p;
                                                        cf <= p[15:8]!=8'd0;
                                                        vf <= p[15:8]!=8'd0;
                                                end
                                        end
                                3'd6,3'd7:
                                        begin
                                                $display("state <= DIVIDE1");
                                                state <= DIVIDE1;
                                        end
                                default:        ;
                                endcase
                        end
 
                `INC_REG:
                        begin
                                state <= IFETCH;
                                wrregs <= 1'b1;
                                w <= 1'b1;
                                res <= alu_o;
                                pf <= pres;
                                af <= carry   (1'b0,a[3],b[3],alu_o[3]);
                                vf <= overflow(1'b0,a[15],b[15],resnw);
                                sf <= resnw;
                                zf <= reszw;
                        end
                `DEC_REG:
                        begin
                                state <= IFETCH;
                                wrregs <= 1'b1;
                                w <= 1'b1;
                                res <= alu_o;
                                pf <= pres;
                                af <= carry   (1'b1,a[3],b[3],alu_o[3]);
                                vf <= overflow(1'b1,a[15],b[15],resnw);
                                sf <= resnw;
                                zf <= reszw;
                        end
//              `IMUL:
//                      begin
//                              state <= IFETCH;
//                              wrregs <= 1'b1;
//                              w <= 1'b1;
//                              rrr <= 3'd0;
//                              res <= alu_o;
//                              if (w) begin
//                                      cf <= wp[31:16]!={16{resnw}};
//                                      vf <= wp[31:16]!={16{resnw}};
//                                      dx <= wp[31:16];
//                              end
//                              else begin
//                                      cf <= ah!={8{resnb}};
//                                      vf <= ah!={8{resnb}};
//                              end
//                      end
 
 
                //-----------------------------------------------------------------
                // Memory Operations
                //-----------------------------------------------------------------
 
                // registers not allowed on LEA
                // invalid opcode
                //
                `LEA:
                        begin
                                w <= 1'b1;
                                res <= ea;
                                if (mod==2'b11) begin
                                        int_num <= 8'h06;
                                        state <= INT;
                                end
                                else begin
                                        state <= IFETCH;
                                        wrregs <= 1'b1;
                                end
                        end
                `LDS:
                        begin
                                wrsregs <= 1'b1;
                                res <= alu_o;
                                rrr <= 3'd3;
                                state <= IFETCH;
                        end
                `LES:
                        begin
                                wrsregs <= 1'b1;
                                res <= alu_o;
                                rrr <= 3'd0;
                                state <= IFETCH;
                        end
 
                `MOV_RR8,`MOV_RR16,
                `MOV_MR,
                `MOV_M2AL,`MOV_M2AX,
                `MOV_I2AL,`MOV_I2DL,`MOV_I2CL,`MOV_I2BL,`MOV_I2AH,`MOV_I2DH,`MOV_I2CH,`MOV_I2BH,
                `MOV_I2AX,`MOV_I2DX,`MOV_I2CX,`MOV_I2BX,`MOV_I2SP,`MOV_I2BP,`MOV_I2SI,`MOV_I2DI:
                        begin
                                state <= IFETCH;
                                wrregs <= 1'b1;
                                res <= alu_o;
                        end
                `XCHG_MEM:
                        begin
                                wrregs <= 1'b1;
                                if (mod==2'b11) rrr <= rm;
                                res <= alu_o;
                                b <= rrro;
                                state <= mod==2'b11 ? IFETCH : XCHG_MEM;
                        end
                `MOV_I8M,`MOV_I16M:
                        begin
                                res <= alu_o;
                                state <= rrr==3'd0 ? STORE_DATA : INVALID_OPCODE;
                        end
 
                `MOV_S2R:
                        begin
                                w <= 1'b1;
                                rrr <= rm;
                                res <= b;
                                if (mod==2'b11) begin
                                        state <= IFETCH;
                                        wrregs <= 1'b1;
                                end
                                else
                                        state <= STORE_DATA;
                        end
                `MOV_R2S:
                        begin
                                wrsregs <= 1'b1;
                                res <= alu_o;
                                state <= IFETCH;
                        end
 
                `LODSB:
                        begin
                                state <= IFETCH;
                                wrregs <= 1'b1;
                                w <= 1'b0;
                                rrr <= 3'd0;
                                res <= a[7:0];
                                if ( df) si <= si_dec;
                                if (!df) si <= si_inc;
                        end
                `LODSW:
                        begin
                                state <= IFETCH;
                                wrregs <= 1'b1;
                                w <= 1'b1;
                                rrr <= 3'd0;
                                res <= a;
                                if ( df) si <= si - 16'd2;
                                if (!df) si <= si + 16'd2;
                        end
 
                8'hD0,8'hD1,8'hD2,8'hD3,8'hC0,8'hC1:
                        begin
                                state <= IFETCH;
                                wrregs <= 1'b1;
                                rrr <= rm;
                                if (w)
                                        case(rrr)
                                        3'b000: // ROL
                                                begin
                                                        res <= shlo[15:0]|shlo[31:16];
                                                        cf <= bmsb;
                                                        vf <= bmsb^b[14];
                                                end
                                        3'b001: // ROR
                                                begin
                                                        res <= shruo[15:0]|shruo[31:16];
                                                        cf <= b[0];
                                                        vf <= cf^b[15];
                                                end
                                        3'b010: // RCL
                                                begin
                                                        res <= shlco[16:1]|shlco[32:17];
                                                        cf <= b[15];
                                                        vf <= b[15]^b[14];
                                                end
                                        3'b011: // RCR
                                                begin
                                                        res <= shrcuo[15:0]|shrcuo[31:16];
                                                        cf <= b[0];
                                                        vf <= cf^b[15];
                                                end
                                        3'b100: // SHL
                                                begin
                                                        res <= shlo[15:0];
                                                        cf <= shlo[16];
                                                        vf <= b[15]^b[14];
                                                end
                                        3'b101: // SHR
                                                begin
                                                        res <= shruo[31:16];
                                                        cf <= shruo[15];
                                                        vf <= b[15];
                                                end
                                        3'b111: // SAR
                                                begin
                                                        res <= shro;
                                                        cf <= b[0];
                                                        vf <= 1'b0;
                                                end
                                        endcase
                                else
                                        case(rrr)
                                        3'b000: // ROL
                                                begin
                                                        res <= shlo8[7:0]|shlo8[15:8];
                                                        cf <= b[7];
                                                        vf <= b[7]^b[6];
                                                end
                                        3'b001: // ROR
                                                begin
                                                        res <= shruo8[15:8]|shruo8[7:0];
                                                        cf <= b[0];
                                                        vf <= cf^b[7];
                                                end
                                        3'b010: // RCL
                                                begin
                                                        res <= shlco8[8:1]|shlco8[16:9];
                                                        cf <= b[7];
                                                        vf <= b[7]^b[6];
                                                end
                                        3'b011: // RCR
                                                begin
                                                        res <= shrcuo8[15:8]|shrcuo8[7:0];
                                                        cf <= b[0];
                                                        vf <= cf^b[7];
                                                end
                                        3'b100: // SHL
                                                begin
                                                        res <= shlo8[7:0];
                                                        cf <= shlo8[8];
                                                        vf <= b[7]^b[6];
                                                end
                                        3'b101: // SHR
                                                begin
                                                        res <= shruo8[15:8];
                                                        cf <= shruo8[7];
                                                        vf <= b[7];
                                                end
                                        3'b111: // SAR
                                                begin
                                                        res <= shro8;
                                                        cf <= b[0];
                                                        vf <= 1'b0;
                                                end
                                        endcase
                        end
 
                //-----------------------------------------------------------------
                //-----------------------------------------------------------------
                `GRPFF:
                        begin
                                case(rrr)
                                3'b000:         // INC
                                        begin
                                                state <= IFETCH;
                                                wrregs <= 1'b1;
                                                af <= carry   (1'b0,a[3],b[3],alu_o[3]);
                                                vf <= overflow(1'b0,a[15],b[15],alu_o[15]);
                                                w <= 1'b1;
                                                res <= alu_o;
                                                rrr <= rm;
                                                pf <= pres;
                                                sf <= resnw;
                                                zf <= reszw;
                                        end
                                3'b001:         // DEC
                                        begin
                                                state <= IFETCH;
                                                wrregs <= 1'b1;
                                                af <= carry   (1'b1,a[3],b[3],alu_o[3]);
                                                vf <= overflow(1'b1,a[15],b[15],alu_o[15]);
                                                w <= 1'b1;
                                                res <= alu_o;
                                                rrr <= rm;
                                                pf <= pres;
                                                sf <= resnw;
                                                zf <= reszw;
                                        end
                                3'b010: begin sp <= sp_dec; state <= CALL_IN; end
                                // These two should not be reachable here, as they would
                                // be trapped by the EACALC.
                                3'b011: state <= CALL_FIN;      // CALL FAR indirect
                                3'b101: // JMP FAR indirect
                                        begin
                                                ip <= offset;
                                                cs <= selector;
                                                state <= IFETCH;
                                        end
                                3'b110: begin sp <= sp_dec; state <= PUSH; end
                                default:
                                        begin
                                                af <= carry   (1'b0,a[3],b[3],alu_o[3]);
                                                vf <= overflow(1'b0,a[15],b[15],alu_o[15]);
                                        end
                                endcase
                        end
 
                //-----------------------------------------------------------------
                //-----------------------------------------------------------------
                default:
                        state <= IFETCH;
                endcase
        end
 

Line No.	Rev	Author	Line
1	2	robfinch	`// ============================================================================`
2			`// (C) 2009,2010,2012 Robert Finch`
3			`// robfinch<remove>@opencores.org`
4			`//`
5			`// EXECUTE`
6			`// - execute instruction`
7			`//`
8			`//`
9			`// This source file is free software: you can redistribute it and/or modify`
10			`// it under the terms of the GNU Lesser General Public License as published`
11			`// by the Free Software Foundation, either version 3 of the License, or`
12			`// (at your option) any later version.`
13			`//`
14			`// This source file is distributed in the hope that it will be useful,`
15			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
16			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
17			`// GNU General Public License for more details.`
18			`//`
19			`// You should have received a copy of the GNU General Public License`
20			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
21			`//`
22			`//`
23			`// Verilog`
24			`//`
25			`// ============================================================================`
26			`//`
27			`EXECUTE:`
28			`begin`
29			`casex(ir)`
30
31			`EXTOP:
32			`casex(ir2)`
33			`LxDT: state <= FETCH_DESC;
34			`endcase`
35
36			`DAA:
37			`begin`
38			`state <= IFETCH;`
39			`end`
40
41			`ALU_I2R8,`ALU_I2R16,`ADD,`ADD_ALI8,`ADD_AXI16,`ADC,`ADC_ALI8,`ADC_AXI16:
42			`begin`
43			`state <= IFETCH;`
44			`wrregs <= 1'b1;`
45			`res <= alu_o;`
46			`pf <= pres;`
47			`af <= carry (1'b0,a[3],b[3],alu_o[3]);`
48			`cf <= carry (1'b0,amsb,bmsb,resn);`
49			`vf <= overflow(1'b0,amsb,bmsb,resn);`
50			`sf <= resn;`
51			`zf <= resz;`
52			`end`
53
54			`AND,`OR,`XOR,`AND_ALI8,`OR_ALI8,`XOR_ALI8,`AND_AXI16,`OR_AXI16,`XOR_AXI16:
55			`begin`
56			`state <= IFETCH;`
57			`wrregs <= 1'b1;`
58			`res <= alu_o;`
59			`pf <= pres;`
60			`cf <= 1'b0;`
61			`vf <= 1'b0;`
62			`sf <= resn;`
63			`zf <= resz;`
64			`end`
65
66			`TEST:
67			`begin`
68			`state <= IFETCH;`
69			`res <= alu_o;`
70			`pf <= pres;`
71			`cf <= 1'b0;`
72			`vf <= 1'b0;`
73			`sf <= resn;`
74			`zf <= resz;`
75			`end`
76
77			`CMP,`CMP_ALI8,`CMP_AXI16:
78			`begin`
79			`state <= IFETCH;`
80			`pf <= pres;`
81			`af <= carry (1'b1,a[3],b[3],alu_o[3]);`
82			`cf <= carry (1'b1,amsb,bmsb,resn);`
83			`vf <= overflow(1'b1,amsb,bmsb,resn);`
84			`sf <= resn;`
85			`zf <= resz;`
86			`end`
87
88			`SBB,`SUB,`SBB_ALI8,`SUB_ALI8,`SBB_AXI16,`SUB_AXI16:
89			`begin`
90			`wrregs <= 1'b1;`
91			`state <= IFETCH;`
92			`res <= alu_o;`
93			`pf <= pres;`
94			`af <= carry (1'b1,a[3],b[3],alu_o[3]);`
95			`cf <= carry (1'b1,amsb,bmsb,resn);`
96			`vf <= overflow(1'b1,amsb,bmsb,resn);`
97			`sf <= resn;`
98			`zf <= resz;`
99			`end`
100
101			`8'hF6,8'hF7:`
102			`begin`
103			`state <= IFETCH;`
104	6	robfinch	`res <= alu_o;`
105			`case(TTT)`
106			`3'd0: // TEST`
107			`begin`
108			`pf <= pres;`
109			`cf <= 1'b0;`
110			`vf <= 1'b0;`
111			`sf <= resn;`
112			`zf <= resz;`
113			`end`
114			`3'd2: // NOT`
115			`begin`
116			`wrregs <= 1'b1;`
117			`end`
118			`3'd3: // NEG`
119			`begin`
120			`pf <= pres;`
121			`af <= carry (1'b1,1'b0,b[3],alu_o[3]);`
122			`cf <= carry (1'b1,1'b0,bmsb,resn);`
123			`vf <= overflow(1'b1,1'b0,bmsb,resn);`
124			`sf <= resn;`
125			`zf <= resz;`
126			`wrregs <= 1'b1;`
127			`end`
128			`// Normally only a single register update is required, however with`
129			`// multiply word both AX and DX need to be updated. So we bypass the`
130			`// regular update here.`
131			`3'd4:`
132			`begin`
133			`if (w) begin`
134			`ax <= p32[15:0];`
135			`dx <= p32[31:16];`
136			`cf <= p32[31:16]!=16'd0;`
137			`vf <= p32[31:16]!=16'd0;`
138			`end`
139			`else begin`
140			`ax <= p16;`
141			`cf <= p16[15:8]!=8'd0;`
142			`vf <= p16[15:8]!=8'd0;`
143			`end`
144			`end`
145			`3'd5:`
146			`begin`
147			`if (w) begin`
148			`ax <= wp[15:0];`
149			`dx <= wp[31:16];`
150			`cf <= p32[31:16]!=16'd0;`
151			`vf <= p32[31:16]!=16'd0;`
152			`end`
153			`else begin`
154			`ax <= p;`
155			`cf <= p[15:8]!=8'd0;`
156			`vf <= p[15:8]!=8'd0;`
157			`end`
158			`end`
159			`3'd6,3'd7:`
160			`begin`
161	7	robfinch	`$display("state <= DIVIDE1");`
162	6	robfinch	`state <= DIVIDE1;`
163			`end`
164			`default: ;`
165	2	robfinch	`endcase`
166			`end`
167	6	robfinch
168	2	robfinch	`INC_REG:
169			`begin`
170			`state <= IFETCH;`
171			`wrregs <= 1'b1;`
172			`w <= 1'b1;`
173			`res <= alu_o;`
174			`pf <= pres;`
175			`af <= carry (1'b0,a[3],b[3],alu_o[3]);`
176			`vf <= overflow(1'b0,a[15],b[15],resnw);`
177			`sf <= resnw;`
178			`zf <= reszw;`
179			`end`
180			`DEC_REG:
181			`begin`
182			`state <= IFETCH;`
183			`wrregs <= 1'b1;`
184			`w <= 1'b1;`
185			`res <= alu_o;`
186			`pf <= pres;`
187			`af <= carry (1'b1,a[3],b[3],alu_o[3]);`
188			`vf <= overflow(1'b1,a[15],b[15],resnw);`
189			`sf <= resnw;`
190			`zf <= reszw;`
191			`end`
192	8	robfinch	// `IMUL:
193			`// begin`
194			`// state <= IFETCH;`
195			`// wrregs <= 1'b1;`
196			`// w <= 1'b1;`
197			`// rrr <= 3'd0;`
198			`// res <= alu_o;`
199			`// if (w) begin`
200			`// cf <= wp[31:16]!={16{resnw}};`
201			`// vf <= wp[31:16]!={16{resnw}};`
202			`// dx <= wp[31:16];`
203			`// end`
204			`// else begin`
205			`// cf <= ah!={8{resnb}};`
206			`// vf <= ah!={8{resnb}};`
207			`// end`
208			`// end`
209	2	robfinch
210
211			`//-----------------------------------------------------------------`
212			`// Memory Operations`
213			`//-----------------------------------------------------------------`
214
215			`// registers not allowed on LEA`
216			`// invalid opcode`
217			`//`
218			`LEA:
219			`begin`
220			`w <= 1'b1;`
221			`res <= ea;`
222			`if (mod==2'b11) begin`
223			`int_num <= 8'h06;`
224			`state <= INT;`
225			`end`
226			`else begin`
227			`state <= IFETCH;`
228			`wrregs <= 1'b1;`
229			`end`
230			`end`
231			`LDS:
232			`begin`
233			`wrsregs <= 1'b1;`
234			`res <= alu_o;`
235			`rrr <= 3'd3;`
236			`state <= IFETCH;`
237			`end`
238			`LES:
239			`begin`
240			`wrsregs <= 1'b1;`
241			`res <= alu_o;`
242			`rrr <= 3'd0;`
243			`state <= IFETCH;`
244			`end`
245
246			`MOV_RR8,`MOV_RR16,
247			`MOV_MR,
248			`MOV_M2AL,`MOV_M2AX,
249			`MOV_I2AL,`MOV_I2DL,`MOV_I2CL,`MOV_I2BL,`MOV_I2AH,`MOV_I2DH,`MOV_I2CH,`MOV_I2BH,
250			`MOV_I2AX,`MOV_I2DX,`MOV_I2CX,`MOV_I2BX,`MOV_I2SP,`MOV_I2BP,`MOV_I2SI,`MOV_I2DI:
251			`begin`
252			`state <= IFETCH;`
253			`wrregs <= 1'b1;`
254			`res <= alu_o;`
255			`end`
256			`XCHG_MEM:
257			`begin`
258			`wrregs <= 1'b1;`
259			`if (mod==2'b11) rrr <= rm;`
260			`res <= alu_o;`
261			`b <= rrro;`
262			`state <= mod==2'b11 ? IFETCH : XCHG_MEM;`
263			`end`
264			`MOV_I8M,`MOV_I16M:
265			`begin`
266			`res <= alu_o;`
267			`state <= rrr==3'd0 ? STORE_DATA : INVALID_OPCODE;`
268			`end`
269
270			`MOV_S2R:
271			`begin`
272			`w <= 1'b1;`
273			`rrr <= rm;`
274			`res <= b;`
275			`if (mod==2'b11) begin`
276			`state <= IFETCH;`
277			`wrregs <= 1'b1;`
278			`end`
279			`else`
280			`state <= STORE_DATA;`
281			`end`
282			`MOV_R2S:
283			`begin`
284			`wrsregs <= 1'b1;`
285			`res <= alu_o;`
286			`state <= IFETCH;`
287			`end`
288
289			`LODSB:
290			`begin`
291			`state <= IFETCH;`
292			`wrregs <= 1'b1;`
293			`w <= 1'b0;`
294			`rrr <= 3'd0;`
295			`res <= a[7:0];`
296			`if ( df) si <= si_dec;`
297			`if (!df) si <= si_inc;`
298			`end`
299			`LODSW:
300			`begin`
301			`state <= IFETCH;`
302			`wrregs <= 1'b1;`
303			`w <= 1'b1;`
304			`rrr <= 3'd0;`
305			`res <= a;`
306			`if ( df) si <= si - 16'd2;`
307			`if (!df) si <= si + 16'd2;`
308			`end`
309
310			`8'hD0,8'hD1,8'hD2,8'hD3,8'hC0,8'hC1:`
311			`begin`
312			`state <= IFETCH;`
313			`wrregs <= 1'b1;`
314	5	robfinch	`rrr <= rm;`
315	2	robfinch	`if (w)`
316			`case(rrr)`
317			`3'b000: // ROL`
318			`begin`
319	4	robfinch	`res <= shlo[15:0]\|shlo[31:16];`
320	2	robfinch	`cf <= bmsb;`
321			`vf <= bmsb^b[14];`
322			`end`
323			`3'b001: // ROR`
324			`begin`
325	4	robfinch	`res <= shruo[15:0]\|shruo[31:16];`
326	2	robfinch	`cf <= b[0];`
327			`vf <= cf^b[15];`
328			`end`
329			`3'b010: // RCL`
330			`begin`
331	4	robfinch	`res <= shlco[16:1]\|shlco[32:17];`
332	2	robfinch	`cf <= b[15];`
333			`vf <= b[15]^b[14];`
334			`end`
335			`3'b011: // RCR`
336			`begin`
337	4	robfinch	`res <= shrcuo[15:0]\|shrcuo[31:16];`
338	2	robfinch	`cf <= b[0];`
339			`vf <= cf^b[15];`
340			`end`
341			`3'b100: // SHL`
342			`begin`
343	4	robfinch	`res <= shlo[15:0];`
344			`cf <= shlo[16];`
345	2	robfinch	`vf <= b[15]^b[14];`
346			`end`
347			`3'b101: // SHR`
348			`begin`
349	4	robfinch	`res <= shruo[31:16];`
350			`cf <= shruo[15];`
351	2	robfinch	`vf <= b[15];`
352			`end`
353			`3'b111: // SAR`
354			`begin`
355	4	robfinch	`res <= shro;`
356	2	robfinch	`cf <= b[0];`
357			`vf <= 1'b0;`
358			`end`
359			`endcase`
360			`else`
361			`case(rrr)`
362			`3'b000: // ROL`
363			`begin`
364	4	robfinch	`res <= shlo8[7:0]\|shlo8[15:8];`
365	2	robfinch	`cf <= b[7];`
366			`vf <= b[7]^b[6];`
367			`end`
368			`3'b001: // ROR`
369			`begin`
370	4	robfinch	`res <= shruo8[15:8]\|shruo8[7:0];`
371	2	robfinch	`cf <= b[0];`
372			`vf <= cf^b[7];`
373			`end`
374			`3'b010: // RCL`
375			`begin`
376	4	robfinch	`res <= shlco8[8:1]\|shlco8[16:9];`
377	2	robfinch	`cf <= b[7];`
378			`vf <= b[7]^b[6];`
379			`end`
380			`3'b011: // RCR`
381			`begin`
382	4	robfinch	`res <= shrcuo8[15:8]\|shrcuo8[7:0];`
383	2	robfinch	`cf <= b[0];`
384			`vf <= cf^b[7];`
385			`end`
386			`3'b100: // SHL`
387			`begin`
388	4	robfinch	`res <= shlo8[7:0];`
389			`cf <= shlo8[8];`
390	2	robfinch	`vf <= b[7]^b[6];`
391			`end`
392			`3'b101: // SHR`
393			`begin`
394	4	robfinch	`res <= shruo8[15:8];`
395			`cf <= shruo8[7];`
396	2	robfinch	`vf <= b[7];`
397			`end`
398			`3'b111: // SAR`
399			`begin`
400	4	robfinch	`res <= shro8;`
401	2	robfinch	`cf <= b[0];`
402			`vf <= 1'b0;`
403			`end`
404			`endcase`
405			`end`
406
407			`//-----------------------------------------------------------------`
408			`//-----------------------------------------------------------------`
409			`GRPFF:
410			`begin`
411			`case(rrr)`
412			`3'b000: // INC`
413			`begin`
414			`state <= IFETCH;`
415			`wrregs <= 1'b1;`
416			`af <= carry (1'b0,a[3],b[3],alu_o[3]);`
417			`vf <= overflow(1'b0,a[15],b[15],alu_o[15]);`
418			`w <= 1'b1;`
419			`res <= alu_o;`
420			`rrr <= rm;`
421			`pf <= pres;`
422			`sf <= resnw;`
423			`zf <= reszw;`
424			`end`
425			`3'b001: // DEC`
426			`begin`
427			`state <= IFETCH;`
428			`wrregs <= 1'b1;`
429			`af <= carry (1'b1,a[3],b[3],alu_o[3]);`
430			`vf <= overflow(1'b1,a[15],b[15],alu_o[15]);`
431			`w <= 1'b1;`
432			`res <= alu_o;`
433			`rrr <= rm;`
434			`pf <= pres;`
435			`sf <= resnw;`
436			`zf <= reszw;`
437			`end`
438			`3'b010: begin sp <= sp_dec; state <= CALL_IN; end`
439			`// These two should not be reachable here, as they would`
440			`// be trapped by the EACALC.`
441			`3'b011: state <= CALL_FIN; // CALL FAR indirect`
442			`3'b101: // JMP FAR indirect`
443			`begin`
444			`ip <= offset;`
445			`cs <= selector;`
446			`state <= IFETCH;`
447			`end`
448			`3'b110: begin sp <= sp_dec; state <= PUSH; end`
449			`default:`
450			`begin`
451			`af <= carry (1'b0,a[3],b[3],alu_o[3]);`
452			`vf <= overflow(1'b0,a[15],b[15],alu_o[15]);`
453			`end`
454			`endcase`
455			`end`
456
457			`//-----------------------------------------------------------------`
458			`//-----------------------------------------------------------------`
459			`default:`
460			`state <= IFETCH;`
461			`endcase`
462			`end`
463

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