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[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [FETCH_DISP16.v] - Blame information for rev 4

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// ============================================================================
//  FETCH_DISP16
//  - detch 16 bit displacement
//
//
//  2009-2012  Robert Finch
//  robfinch[remove]@opencores.org
//  Stratford
//
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//
//
//  Verilog 
//
// Fetch 16 bit displacement
// ============================================================================
//
FETCH_DISP16:
        begin
                `INITIATE_CODE_READ;
                state <= FETCH_DISP16_ACK;
        end
 
FETCH_DISP16_ACK:
        if (ack_i) begin
                state <= FETCH_DISP16a;
                `PAUSE_CODE_READ
                disp16[7:0] <= dat_i;
        end
 
FETCH_DISP16a:
        begin
                state <= FETCH_DISP16a_ACK;
                `INITIATE_CODE_READ
        end
 
FETCH_DISP16a_ACK:
        if (ack_i) begin
                state <= FETCH_DISP16b;
                `TERMINATE_CODE_READ
                disp16[15:8] <= dat_i;
        end
 
FETCH_DISP16b:
        casex(ir)
 
        //-----------------------------------------------------------------
        // Flow control operations
        //-----------------------------------------------------------------
        `CALL: state <= CALL;
        `JMP: begin ip <= ip + disp16; state <= IFETCH; end
        `JMPS: begin ip <= ip + disp16; state <= IFETCH; end
 
        //-----------------------------------------------------------------
        // Memory Operations
        //-----------------------------------------------------------------
 
        `MOV_AL2M,`MOV_AX2M:
                begin
                        res <= ax;
                        ea <= {seg_reg,`SEG_SHIFT} + disp16;
                        state <= STORE_DATA;
                end
        `MOV_M2AL,`MOV_M2AX:
                begin
                        d <= 1'b0;
                        rrr <= 3'd0;
                        ea <= {seg_reg,`SEG_SHIFT} + disp16;
                        state <= FETCH_DATA;
                end
 
        `MOV_MA:
                case(substate)
                FETCH_DATA:
                        if (hasFetchedData) begin
                                ir <= {4'b0,w,3'b0};
                                wrregs <= 1'b1;
                                res <= disp16;
                                state <= IFETCH;
                        end
                endcase
 
        `MOV_AM:
                begin
                        w <= ir[0];
                        state <= STORE_DATA;
                        ea  <= {ds,`SEG_SHIFT} + disp16;
                        res <= ir[0] ? {ah,al} : {al,al};
                end
        default:        state <= IFETCH;
        endcase

Line No.	Rev	Author	Line
1	2	robfinch	`// ============================================================================`
2			`// FETCH_DISP16`
3			`// - detch 16 bit displacement`
4			`//`
5			`//`
6			`// 2009-2012 Robert Finch`
7			`// robfinch[remove]@opencores.org`
8			`// Stratford`
9			`//`
10			`//`
11			`// This source file is free software: you can redistribute it and/or modify`
12			`// it under the terms of the GNU Lesser General Public License as published`
13			`// by the Free Software Foundation, either version 3 of the License, or`
14			`// (at your option) any later version.`
15			`//`
16			`// This source file is distributed in the hope that it will be useful,`
17			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
18			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
19			`// GNU General Public License for more details.`
20			`//`
21			`// You should have received a copy of the GNU General Public License`
22			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
23			`//`
24			`//`
25			`// Verilog`
26			`//`
27			`// Fetch 16 bit displacement`
28			`// ============================================================================`
29			`//`
30			`FETCH_DISP16:`
31			`begin`
32			`INITIATE_CODE_READ;
33			`state <= FETCH_DISP16_ACK;`
34			`end`
35
36			`FETCH_DISP16_ACK:`
37			`if (ack_i) begin`
38			`state <= FETCH_DISP16a;`
39			`PAUSE_CODE_READ
40			`disp16[7:0] <= dat_i;`
41			`end`
42
43			`FETCH_DISP16a:`
44			`begin`
45			`state <= FETCH_DISP16a_ACK;`
46			`INITIATE_CODE_READ
47			`end`
48
49			`FETCH_DISP16a_ACK:`
50			`if (ack_i) begin`
51			`state <= FETCH_DISP16b;`
52			`TERMINATE_CODE_READ
53			`disp16[15:8] <= dat_i;`
54			`end`
55
56			`FETCH_DISP16b:`
57			`casex(ir)`
58
59			`//-----------------------------------------------------------------`
60			`// Flow control operations`
61			`//-----------------------------------------------------------------`
62			`CALL: state <= CALL;
63			`JMP: begin ip <= ip + disp16; state <= IFETCH; end
64			`JMPS: begin ip <= ip + disp16; state <= IFETCH; end
65
66			`//-----------------------------------------------------------------`
67			`// Memory Operations`
68			`//-----------------------------------------------------------------`
69
70			`MOV_AL2M,`MOV_AX2M:
71			`begin`
72			`res <= ax;`
73			ea <= {seg_reg,`SEG_SHIFT} + disp16;
74			`state <= STORE_DATA;`
75			`end`
76			`MOV_M2AL,`MOV_M2AX:
77			`begin`
78			`d <= 1'b0;`
79			`rrr <= 3'd0;`
80			ea <= {seg_reg,`SEG_SHIFT} + disp16;
81			`state <= FETCH_DATA;`
82			`end`
83
84			`MOV_MA:
85			`case(substate)`
86			`FETCH_DATA:`
87			`if (hasFetchedData) begin`
88			`ir <= {4'b0,w,3'b0};`
89			`wrregs <= 1'b1;`
90			`res <= disp16;`
91			`state <= IFETCH;`
92			`end`
93			`endcase`
94
95			`MOV_AM:
96			`begin`
97			`w <= ir[0];`
98			`state <= STORE_DATA;`
99			ea <= {ds,`SEG_SHIFT} + disp16;
100			`res <= ir[0] ? {ah,al} : {al,al};`
101			`end`
102			`default: state <= IFETCH;`
103			`endcase`

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[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [FETCH_DISP16.v] - Blame information for rev 4