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[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [FETCH_DISP16.v] - Blame information for rev 4

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Line No. Rev Author Line
1 2 robfinch
// ============================================================================
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//  FETCH_DISP16
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//  - detch 16 bit displacement
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//
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//
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//  2009-2012  Robert Finch
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//  robfinch[remove]@opencores.org
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//  Stratford
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//
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//
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// This source file is free software: you can redistribute it and/or modify 
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// it under the terms of the GNU Lesser General Public License as published 
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// by the Free Software Foundation, either version 3 of the License, or     
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// (at your option) any later version.                                      
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//                                                                          
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// This source file is distributed in the hope that it will be useful,      
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// but WITHOUT ANY WARRANTY; without even the implied warranty of           
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
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// GNU General Public License for more details.                             
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//                                                                          
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// You should have received a copy of the GNU General Public License        
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
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//
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//
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//  Verilog 
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//
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// Fetch 16 bit displacement
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// ============================================================================
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//
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FETCH_DISP16:
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        begin
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                `INITIATE_CODE_READ;
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                state <= FETCH_DISP16_ACK;
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        end
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FETCH_DISP16_ACK:
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        if (ack_i) begin
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                state <= FETCH_DISP16a;
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                `PAUSE_CODE_READ
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                disp16[7:0] <= dat_i;
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        end
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FETCH_DISP16a:
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        begin
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                state <= FETCH_DISP16a_ACK;
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                `INITIATE_CODE_READ
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        end
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FETCH_DISP16a_ACK:
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        if (ack_i) begin
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                state <= FETCH_DISP16b;
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                `TERMINATE_CODE_READ
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                disp16[15:8] <= dat_i;
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        end
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FETCH_DISP16b:
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        casex(ir)
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        //-----------------------------------------------------------------
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        // Flow control operations
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        //-----------------------------------------------------------------
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        `CALL: state <= CALL;
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        `JMP: begin ip <= ip + disp16; state <= IFETCH; end
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        `JMPS: begin ip <= ip + disp16; state <= IFETCH; end
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        //-----------------------------------------------------------------
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        // Memory Operations
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        //-----------------------------------------------------------------
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        `MOV_AL2M,`MOV_AX2M:
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                begin
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                        res <= ax;
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                        ea <= {seg_reg,`SEG_SHIFT} + disp16;
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                        state <= STORE_DATA;
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                end
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        `MOV_M2AL,`MOV_M2AX:
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                begin
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                        d <= 1'b0;
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                        rrr <= 3'd0;
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                        ea <= {seg_reg,`SEG_SHIFT} + disp16;
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                        state <= FETCH_DATA;
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                end
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        `MOV_MA:
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                case(substate)
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                FETCH_DATA:
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                        if (hasFetchedData) begin
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                                ir <= {4'b0,w,3'b0};
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                                wrregs <= 1'b1;
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                                res <= disp16;
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                                state <= IFETCH;
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                        end
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                endcase
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        `MOV_AM:
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                begin
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                        w <= ir[0];
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                        state <= STORE_DATA;
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                        ea  <= {ds,`SEG_SHIFT} + disp16;
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                        res <= ir[0] ? {ah,al} : {al,al};
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                end
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        default:        state <= IFETCH;
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        endcase

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