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[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [FETCH_OFFSET_AND_SEGMENT.v] - Blame information for rev 3

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// ============================================================================
//  FETCH_OFFSET_AND_SEGMENT.v
//  - Fetch 16 bit offset
//  - Fetch 16 bit segment
//
//
//  2009,2010,2012  Robert Finch
//  robfinch[remove]@opencores.org
//  Stratford
//
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//
//
//  Verilog 
//
// ============================================================================
//
//
FETCH_OFFSET:
        begin
                lock_o <= 1'b1;
                `INITIATE_CODE_READ
                state <= FETCH_OFFSET1;
        end
FETCH_OFFSET1:
        if (ack_i) begin
                `PAUSE_CODE_READ
                offset[7:0] <= dat_i;
                state <= FETCH_OFFSET2;
        end
FETCH_OFFSET2:
        begin
                `CONTINUE_CODE_READ
                state <= FETCH_OFFSET3;
        end
FETCH_OFFSET3:
        if (ack_i) begin
                `TERMINATE_CODE_READ
                offset[15:8] <= dat_i;
                state <= FETCH_SEGMENT;
        end
FETCH_SEGMENT:
        begin
                `INITIATE_CODE_READ
                state <= FETCH_SEGMENT1;
        end
FETCH_SEGMENT1:
        if (ack_i) begin
                `PAUSE_CODE_READ
                state <= FETCH_SEGMENT2;
                selector[7:0] <= dat_i;
        end
FETCH_SEGMENT2:
        begin
                `CONTINUE_CODE_READ
                state <= FETCH_SEGMENT3;
        end
FETCH_SEGMENT3:
        if (ack_i) begin
                `TERMINATE_CODE_READ
                selector[15:8] <= dat_i;
                if (ir==`CALLF)
                        state <= CALLF;
                else
                        state <= JMPF;
        end
JMPF:
        begin
                cs <= selector;
                ip <= offset;
                state <= IFETCH;
        end
 

Line No.	Rev	Author	Line
1	2	robfinch	`// ============================================================================`
2			`// FETCH_OFFSET_AND_SEGMENT.v`
3			`// - Fetch 16 bit offset`
4			`// - Fetch 16 bit segment`
5			`//`
6			`//`
7			`// 2009,2010,2012 Robert Finch`
8			`// robfinch[remove]@opencores.org`
9			`// Stratford`
10			`//`
11			`//`
12			`// This source file is free software: you can redistribute it and/or modify`
13			`// it under the terms of the GNU Lesser General Public License as published`
14			`// by the Free Software Foundation, either version 3 of the License, or`
15			`// (at your option) any later version.`
16			`//`
17			`// This source file is distributed in the hope that it will be useful,`
18			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
19			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
20			`// GNU General Public License for more details.`
21			`//`
22			`// You should have received a copy of the GNU General Public License`
23			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
24			`//`
25			`//`
26			`// Verilog`
27			`//`
28			`// ============================================================================`
29			`//`
30			`//`
31			`FETCH_OFFSET:`
32			`begin`
33			`lock_o <= 1'b1;`
34			`INITIATE_CODE_READ
35			`state <= FETCH_OFFSET1;`
36			`end`
37			`FETCH_OFFSET1:`
38			`if (ack_i) begin`
39			`PAUSE_CODE_READ
40			`offset[7:0] <= dat_i;`
41			`state <= FETCH_OFFSET2;`
42			`end`
43			`FETCH_OFFSET2:`
44			`begin`
45			`CONTINUE_CODE_READ
46			`state <= FETCH_OFFSET3;`
47			`end`
48			`FETCH_OFFSET3:`
49			`if (ack_i) begin`
50			`TERMINATE_CODE_READ
51			`offset[15:8] <= dat_i;`
52			`state <= FETCH_SEGMENT;`
53			`end`
54			`FETCH_SEGMENT:`
55			`begin`
56			`INITIATE_CODE_READ
57			`state <= FETCH_SEGMENT1;`
58			`end`
59			`FETCH_SEGMENT1:`
60			`if (ack_i) begin`
61			`PAUSE_CODE_READ
62			`state <= FETCH_SEGMENT2;`
63			`selector[7:0] <= dat_i;`
64			`end`
65			`FETCH_SEGMENT2:`
66			`begin`
67			`CONTINUE_CODE_READ
68			`state <= FETCH_SEGMENT3;`
69			`end`
70			`FETCH_SEGMENT3:`
71			`if (ack_i) begin`
72			`TERMINATE_CODE_READ
73			`selector[15:8] <= dat_i;`
74			if (ir==`CALLF)
75			`state <= CALLF;`
76			`else`
77			`state <= JMPF;`
78			`end`
79			`JMPF:`
80			`begin`
81			`cs <= selector;`
82			`ip <= offset;`
83			`state <= IFETCH;`
84			`end`
85

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[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [FETCH_OFFSET_AND_SEGMENT.v] - Blame information for rev 3