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[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [INSB.v] - Blame information for rev 4

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Line No. Rev Author Line
1 2 robfinch
// This source file is free software: you can redistribute it and/or modify 
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// it under the terms of the GNU Lesser General Public License as published 
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// by the Free Software Foundation, either version 3 of the License, or     
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// (at your option) any later version.                                      
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//                                                                          
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// This source file is distributed in the hope that it will be useful,      
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// but WITHOUT ANY WARRANTY; without even the implied warranty of           
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
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// GNU General Public License for more details.                             
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//                                                                          
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// You should have received a copy of the GNU General Public License        
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
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//
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INSB:
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`include "check_for_ints.v"
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        else if (repdone)
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                state <= IFETCH;
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        else if (!cyc_o) begin
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                cyc_type <= `CT_RDIO;
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                cyc_o <= 1'b1;
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                stb_o <= 1'b1;
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                adr_o <= {`SEG_SHIFT,dx};
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        end
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        else if (ack_i) begin
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                cyc_type <= `CT_PASSIVE;
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                cyc_o <= 1'b0;
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                stb_o <= 1'b0;
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                res[7:0] <= dat_i;
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                state <= INSB2;
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        end
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INSB2:
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        if (!cyc_o) begin
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                cyc_type <= `CT_WRMEM;
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                cyc_o <= 1'b1;
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                stb_o <= 1'b1;
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                adr_o <= esdi;
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                dat_o <= res[7:0];
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                we_o <= 1'b1;
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        end
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        else if (ack_i) begin
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                cyc_type <= `CT_PASSIVE;
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                cyc_o <= 1'b0;
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                stb_o <= 1'b0;
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                we_o <= 1'b0;
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                if (df)
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                        di <= di - 16'd1;
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                else
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                        di <= di + 16'd1;
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                if (repz|repnz) cx <= cx_dec;
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                state <= repz|repnz ? INSB : IFETCH;
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        end

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