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[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [INT.v] - Blame information for rev 4

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// ============================================================================
//  INT.v
//  - Interrupt handling
//
//
//  2009-2012  Robert Finch
//  robfinch[remove]@opencores.org
//  Stratford
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//
//
//  Verilog 
//
// - bus is locked if immediate value is unaligned in memory
// - immediate values are the last operand to be fetched, hence
//   the state machine can transition into the EXECUTE state.
// - we also know the immediate value can't be the target of an
//   operation.
// ============================================================================
//
// Fetch interrupt number from instruction stream
//
INT:
        begin
                `INITIATE_CODE_READ
                lock_o <= 1'b1;
                sp <= sp_dec;           // pre-decrement
                state <= INT1;
        end
INT1:
        if (ack_i) begin
                `PAUSE_CODE_READ
                int_num <= dat_i;
                state <= INT2;
        end
INT2:
        begin
                cyc_type <= `CT_RDMEM;
                lock_o <= 1'b1;
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                we_o  <= 1'b0;
                adr_o <= {int_num,2'b00};
                state <= INT3;
        end
INT3:
        if (ack_i) begin
                cyc_type <= `CT_PASSIVE;
                stb_o <= 1'b0;
                offset[7:0] <= dat_i;
                state <= INT4;
        end
INT4:
        begin
                cyc_type <= `CT_RDMEM;
                stb_o <= 1'b1;
                adr_o <= adr_o_inc;
                state <= INT5;
        end
INT5:
        if (ack_i) begin
                cyc_type <= `CT_PASSIVE;
                stb_o <= 1'b0;
                offset[15:8] <= dat_i;
                state <= INT6;
        end
INT6:
        if (!stb_o) begin
                cyc_type <= `CT_RDMEM;
                stb_o <= 1'b1;
                adr_o <= adr_o_inc;
        end
        else if (ack_i) begin
                cyc_type <= `CT_PASSIVE;
                stb_o <= 1'b0;
                state <= INT7;
                selector[7:0] <= dat_i;
        end
INT7:
        if (!stb_o) begin
                cyc_type <= `CT_RDMEM;
                stb_o <= 1'b1;
                adr_o <= adr_o_inc;
        end
        else if (ack_i) begin
                cyc_type <= `CT_PASSIVE;
                lock_o <= 1'b0;
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                state <= INT8;
                selector[15:8] <= dat_i;
        end
INT8:
        if (!cyc_o) begin
                `INITIATE_STACK_WRITE
                lock_o <= 1'b1;
                dat_o <= flags[15:8];
        end
        else if (ack_i) begin
                cyc_type <= `CT_PASSIVE;
                sp <= sp_dec;
                state <= INT9;
                stb_o <= 1'b0;
                we_o  <= 1'b0;
        end
INT9:
        if (!stb_o) begin
                cyc_type <= `CT_WRMEM;
                stb_o <= 1'b1;
                we_o  <= 1'b1;
                adr_o <= sssp;
                dat_o <= flags[7:0];
        end
        else if (ack_i) begin
                cyc_type <= `CT_PASSIVE;
                sp <= sp_dec;
                state <= INT10;
                stb_o <= 1'b0;
                we_o  <= 1'b0;
                ie <= 1'b0;
                tf <= 1'b0;
        end
INT10:
        if (!stb_o) begin
                cyc_type <= `CT_WRMEM;
                stb_o <= 1'b1;
                we_o  <= 1'b1;
                adr_o <= sssp;
                dat_o <= cs[15:8];
        end
        else if (ack_i) begin
                cyc_type <= `CT_PASSIVE;
                sp <= sp_dec;
                state <= INT11;
                stb_o <= 1'b0;
                we_o  <= 1'b0;
        end
INT11:
        if (!stb_o) begin
                cyc_type <= `CT_WRMEM;
                stb_o <= 1'b1;
                we_o  <= 1'b1;
                adr_o <= sssp;
                dat_o <= cs[7:0];
        end
        else if (ack_i) begin
                cyc_type <= `CT_PASSIVE;
                sp <= sp_dec;
                state <= INT12;
                stb_o <= 1'b0;
                we_o  <= 1'b0;
        end
INT12:
        if (!stb_o) begin
                cyc_type <= `CT_WRMEM;
                stb_o <= 1'b1;
                we_o  <= 1'b1;
                adr_o <= sssp;
                dat_o <= ir_ip[15:8];
        end
        else if (ack_i) begin
                cyc_type <= `CT_PASSIVE;
                sp <= sp_dec;
                state <= INT13;
                stb_o <= 1'b0;
                we_o  <= 1'b0;
        end
INT13:
        if (!stb_o) begin
                cyc_type <= `CT_WRMEM;
                stb_o <= 1'b1;
                we_o  <= 1'b1;
                adr_o <= sssp;
                dat_o <= ir_ip[7:0];
        end
        else if (ack_i) begin
                cyc_type <= `CT_PASSIVE;
                state <= IFETCH;
                lock_o <= 1'b0;
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                we_o  <= 1'b0;
                cs <= selector;
                ip <= offset;
        end

Line No.	Rev	Author	Line
1	2	robfinch	`// ============================================================================`
2			`// INT.v`
3			`// - Interrupt handling`
4			`//`
5			`//`
6			`// 2009-2012 Robert Finch`
7			`// robfinch[remove]@opencores.org`
8			`// Stratford`
9			`//`
10			`// This source file is free software: you can redistribute it and/or modify`
11			`// it under the terms of the GNU Lesser General Public License as published`
12			`// by the Free Software Foundation, either version 3 of the License, or`
13			`// (at your option) any later version.`
14			`//`
15			`// This source file is distributed in the hope that it will be useful,`
16			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
17			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
18			`// GNU General Public License for more details.`
19			`//`
20			`// You should have received a copy of the GNU General Public License`
21			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
22			`//`
23			`//`
24			`// Verilog`
25			`//`
26			`// - bus is locked if immediate value is unaligned in memory`
27			`// - immediate values are the last operand to be fetched, hence`
28			`// the state machine can transition into the EXECUTE state.`
29			`// - we also know the immediate value can't be the target of an`
30			`// operation.`
31			`// ============================================================================`
32			`//`
33			`// Fetch interrupt number from instruction stream`
34			`//`
35			`INT:`
36			`begin`
37			`INITIATE_CODE_READ
38			`lock_o <= 1'b1;`
39			`sp <= sp_dec; // pre-decrement`
40			`state <= INT1;`
41			`end`
42			`INT1:`
43			`if (ack_i) begin`
44			`PAUSE_CODE_READ
45			`int_num <= dat_i;`
46			`state <= INT2;`
47			`end`
48			`INT2:`
49			`begin`
50			cyc_type <= `CT_RDMEM;
51			`lock_o <= 1'b1;`
52			`cyc_o <= 1'b1;`
53			`stb_o <= 1'b1;`
54			`we_o <= 1'b0;`
55			`adr_o <= {int_num,2'b00};`
56			`state <= INT3;`
57			`end`
58			`INT3:`
59			`if (ack_i) begin`
60			cyc_type <= `CT_PASSIVE;
61			`stb_o <= 1'b0;`
62			`offset[7:0] <= dat_i;`
63			`state <= INT4;`
64			`end`
65			`INT4:`
66			`begin`
67			cyc_type <= `CT_RDMEM;
68			`stb_o <= 1'b1;`
69			`adr_o <= adr_o_inc;`
70			`state <= INT5;`
71			`end`
72			`INT5:`
73			`if (ack_i) begin`
74			cyc_type <= `CT_PASSIVE;
75			`stb_o <= 1'b0;`
76			`offset[15:8] <= dat_i;`
77			`state <= INT6;`
78			`end`
79			`INT6:`
80			`if (!stb_o) begin`
81			cyc_type <= `CT_RDMEM;
82			`stb_o <= 1'b1;`
83			`adr_o <= adr_o_inc;`
84			`end`
85			`else if (ack_i) begin`
86			cyc_type <= `CT_PASSIVE;
87			`stb_o <= 1'b0;`
88			`state <= INT7;`
89			`selector[7:0] <= dat_i;`
90			`end`
91			`INT7:`
92			`if (!stb_o) begin`
93			cyc_type <= `CT_RDMEM;
94			`stb_o <= 1'b1;`
95			`adr_o <= adr_o_inc;`
96			`end`
97			`else if (ack_i) begin`
98			cyc_type <= `CT_PASSIVE;
99			`lock_o <= 1'b0;`
100			`cyc_o <= 1'b0;`
101			`stb_o <= 1'b0;`
102			`state <= INT8;`
103			`selector[15:8] <= dat_i;`
104			`end`
105			`INT8:`
106			`if (!cyc_o) begin`
107			`INITIATE_STACK_WRITE
108			`lock_o <= 1'b1;`
109			`dat_o <= flags[15:8];`
110			`end`
111			`else if (ack_i) begin`
112			cyc_type <= `CT_PASSIVE;
113			`sp <= sp_dec;`
114			`state <= INT9;`
115			`stb_o <= 1'b0;`
116			`we_o <= 1'b0;`
117			`end`
118			`INT9:`
119			`if (!stb_o) begin`
120			cyc_type <= `CT_WRMEM;
121			`stb_o <= 1'b1;`
122			`we_o <= 1'b1;`
123			`adr_o <= sssp;`
124			`dat_o <= flags[7:0];`
125			`end`
126			`else if (ack_i) begin`
127			cyc_type <= `CT_PASSIVE;
128			`sp <= sp_dec;`
129			`state <= INT10;`
130			`stb_o <= 1'b0;`
131			`we_o <= 1'b0;`
132			`ie <= 1'b0;`
133			`tf <= 1'b0;`
134			`end`
135			`INT10:`
136			`if (!stb_o) begin`
137			cyc_type <= `CT_WRMEM;
138			`stb_o <= 1'b1;`
139			`we_o <= 1'b1;`
140			`adr_o <= sssp;`
141			`dat_o <= cs[15:8];`
142			`end`
143			`else if (ack_i) begin`
144			cyc_type <= `CT_PASSIVE;
145			`sp <= sp_dec;`
146			`state <= INT11;`
147			`stb_o <= 1'b0;`
148			`we_o <= 1'b0;`
149			`end`
150			`INT11:`
151			`if (!stb_o) begin`
152			cyc_type <= `CT_WRMEM;
153			`stb_o <= 1'b1;`
154			`we_o <= 1'b1;`
155			`adr_o <= sssp;`
156			`dat_o <= cs[7:0];`
157			`end`
158			`else if (ack_i) begin`
159			cyc_type <= `CT_PASSIVE;
160			`sp <= sp_dec;`
161			`state <= INT12;`
162			`stb_o <= 1'b0;`
163			`we_o <= 1'b0;`
164			`end`
165			`INT12:`
166			`if (!stb_o) begin`
167			cyc_type <= `CT_WRMEM;
168			`stb_o <= 1'b1;`
169			`we_o <= 1'b1;`
170			`adr_o <= sssp;`
171			`dat_o <= ir_ip[15:8];`
172			`end`
173			`else if (ack_i) begin`
174			cyc_type <= `CT_PASSIVE;
175			`sp <= sp_dec;`
176			`state <= INT13;`
177			`stb_o <= 1'b0;`
178			`we_o <= 1'b0;`
179			`end`
180			`INT13:`
181			`if (!stb_o) begin`
182			cyc_type <= `CT_WRMEM;
183			`stb_o <= 1'b1;`
184			`we_o <= 1'b1;`
185			`adr_o <= sssp;`
186			`dat_o <= ir_ip[7:0];`
187			`end`
188			`else if (ack_i) begin`
189			cyc_type <= `CT_PASSIVE;
190			`state <= IFETCH;`
191			`lock_o <= 1'b0;`
192			`cyc_o <= 1'b0;`
193			`stb_o <= 1'b0;`
194			`we_o <= 1'b0;`
195			`cs <= selector;`
196			`ip <= offset;`
197			`end`

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[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [INT.v] - Blame information for rev 4