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[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [INW.v] - Blame information for rev 3

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Line No. Rev Author Line
1 2 robfinch
// ============================================================================
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//  INW.v
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//  - Fetch data from IO.
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//
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//
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//  2009,2010,2012  Robert Finch
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//  robfinch@opencores.org
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//  Stratford
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//
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//  
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// This source file is free software: you can redistribute it and/or modify 
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// it under the terms of the GNU Lesser General Public License as published 
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// by the Free Software Foundation, either version 3 of the License, or     
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// (at your option) any later version.                                      
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//                                                                          
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// This source file is distributed in the hope that it will be useful,      
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// but WITHOUT ANY WARRANTY; without even the implied warranty of           
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
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// GNU General Public License for more details.                             
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//                                                                          
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// You should have received a copy of the GNU General Public License        
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
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//
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//
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//
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//  Verilog 
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//
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// ============================================================================
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//
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INW:
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        begin
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                `INITIATE_CODE_READ
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                state <= INW1;
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        end
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INW1:
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        if (ack_i) begin
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                `TERMINATE_CODE_READ
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                ea <= {12'h000,dat_i};
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                state <= INW2;
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        end
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INW2:
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        begin
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                cyc_type <= `CT_RDIO;
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                mio_o <= 1'b0;
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                cyc_o <= 1'b1;
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                stb_o <= 1'b1;
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                we_o  <= 1'b0;
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                adr_o <= ea;
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                state <= INW3;
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        end
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INW3:
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        if (ack_i) begin
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                cyc_type <= `CT_PASSIVE;
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                mio_o <= 1'b1;
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                stb_o <= 1'b0;
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                res[7:0] <= dat_i;
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                state <= INW4;
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        end
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INW4:
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        begin
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                cyc_type <= `CT_RDIO;
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                mio_o <= 1'b0;
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                stb_o <= 1'b1;
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                adr_o <= ea_inc;
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                state <= INW5;
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        end
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INW5:
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        if (ack_i) begin
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                cyc_type <= `CT_PASSIVE;
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                mio_o <= 1'b1;
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                cyc_o <= 1'b0;
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                stb_o <= 1'b0;
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                we_o  <= 1'b0;
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                wrregs <= 1'b1;
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                w <= 1'b1;
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                rrr <= 3'd0;
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                res[15:8] <= dat_i;
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                state <= IFETCH;
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        end

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