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[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [LODS.v] - Blame information for rev 3

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Line No. Rev Author Line
1 2 robfinch
//=============================================================================
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//  LODS
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//  Fetch string data from memory.
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//
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//
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//  2009,2010 Robert Finch
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//  Stratford
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//  robfinch<remove>@opencores.org
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//
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//
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// This source file is free software: you can redistribute it and/or modify 
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// it under the terms of the GNU Lesser General Public License as published 
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// by the Free Software Foundation, either version 3 of the License, or     
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// (at your option) any later version.                                      
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//                                                                          
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// This source file is distributed in the hope that it will be useful,      
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// but WITHOUT ANY WARRANTY; without even the implied warranty of           
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
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// GNU General Public License for more details.                             
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//                                                                          
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// You should have received a copy of the GNU General Public License        
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
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//
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//=============================================================================
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//
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LODS:
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        if (w && (si==16'hFFFF) && !df) begin
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                ir <= `NOP;
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                int_num <= 8'd13;
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                state <= INT1;
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        end
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        else begin
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                cyc_type <= `CT_RDMEM;
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                lock_o <= w;
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                cyc_o <= 1'b1;
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                stb_o <= 1'b1;
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                we_o  <= 1'b0;
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                adr_o <= {seg_reg,`SEG_SHIFT} + si;
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                state <= LODS_NACK;
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        end
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LODS_NACK:
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        if (ack_i) begin
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                cyc_type <= `CT_PASSIVE;
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                lock_o <= w;
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                cyc_o <= w;
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                stb_o <= 1'b0;
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                if (df) begin
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                        si <= si_dec;
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                        if (w)
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                                b[15:8] <= dat_i;
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                        else begin
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                                b[ 7:0] <= dat_i;
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                                b[15:8] <= {8{dat_i[7]}};
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                        end
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                end
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                else begin
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                        si <= si_inc;
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                        b[ 7:0] <= dat_i;
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                        b[15:8] <= {8{dat_i[7]}};
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                end
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                state <= w ? LODS1 : EXECUTE;
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        end
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LODS1:
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        begin
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                cyc_type <= `CT_RDMEM;
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                stb_o <= 1'b1;
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                adr_o <= {seg_reg,`SEG_SHIFT} + si;
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                state <= LODS1_NACK;
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        end
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LODS1_NACK:
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        if (ack_i) begin
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                cyc_type <= `CT_PASSIVE;
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                lock_o <= 1'b0;
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                cyc_o <= 1'b0;
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                stb_o <= 1'b0;
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                if (df) begin
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                        si <= si_dec;
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                        b[7:0] <= dat_i;
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                end
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                else begin
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                        si <= si_inc;
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                        b[15:8] <= dat_i;
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                end
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                state <= EXECUTE;
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        end
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