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[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [MOVS.v] - Blame information for rev 4

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//=============================================================================
//  MOVSB,MOVSW
//  - moves a byte at a time to account for both bytes and words
//
//
//  2009-2012 Robert Finch
//  Stratford
//  robfinch<remove>@opencores.org
//
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//
//=============================================================================
//
MOVS:
`include "check_for_ints.v"
        else if (w && (si==16'hFFFF)) begin
                ir <= `NOP;
                int_num <= 8'd13;
                state <= INT1;
        end
        else if ((repz|repnz) & cxz)
                state <= IFETCH;
        else begin
                if (!cyc_o) begin
                        cyc_type <= `CT_RDMEM;
                        lock_o <= w;
                        cyc_o <= 1'b1;
                        stb_o <= 1'b1;
                        we_o  <= 1'b0;
                        adr_o <= dssi;
                end
                else if (ack_i) begin
                        cyc_type <= `CT_PASSIVE;
                        state <= w ? MOVS1 : MOVS3;
                        cyc_o <= 1'b0;
                        stb_o <= 1'b0;
                        a[7:0] <= dat_i;
                        si <= df ? si_dec : si_inc;
                end
        end
MOVS1:
        if (!cyc_o) begin
                cyc_type <= `CT_WRMEM;
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                we_o  <= 1'b1;
                adr_o <= esdi;
                dat_o <= a[7:0];
        end
        else if (ack_i) begin
                cyc_type <= `CT_PASSIVE;
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                we_o  <= 1'b0;
                di <= df ? di_dec : di_inc;
                state <= MOVS2;
        end
MOVS2:
        begin
                cyc_type <= `CT_RDMEM;
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                we_o  <= 1'b0;
                adr_o <= dssi;
                state <= MOVS3;
        end
MOVS3:
        if (ack_i) begin
                cyc_type <= `CT_PASSIVE;
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                a[7:0] <= dat_i;
                si <= df ? si_dec : si_inc;
                state <= MOVS4;
        end
MOVS4:
        begin
                cyc_type <= `CT_WRMEM;
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                we_o  <= 1'b1;
                adr_o <= esdi;
                dat_o <= a[7:0];
                state <= MOVS5;
        end
MOVS5:
        if (ack_i) begin
                cyc_type <= `CT_PASSIVE;
                lock_o <= 1'b0;
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                we_o  <= 1'b0;
                di <= df ? di_dec : di_inc;
                if (repz|repnz) begin
                        cx <= cx_dec;
                        state <= MOVS;
                end
                else
                        state <= IFETCH;
        end

Line No.	Rev	Author	Line
1	2	robfinch	`//=============================================================================`
2			`// MOVSB,MOVSW`
3			`// - moves a byte at a time to account for both bytes and words`
4			`//`
5			`//`
6			`// 2009-2012 Robert Finch`
7			`// Stratford`
8			`// robfinch<remove>@opencores.org`
9			`//`
10			`//`
11			`// This source file is free software: you can redistribute it and/or modify`
12			`// it under the terms of the GNU Lesser General Public License as published`
13			`// by the Free Software Foundation, either version 3 of the License, or`
14			`// (at your option) any later version.`
15			`//`
16			`// This source file is distributed in the hope that it will be useful,`
17			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
18			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
19			`// GNU General Public License for more details.`
20			`//`
21			`// You should have received a copy of the GNU General Public License`
22			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
23			`//`
24			`//=============================================================================`
25			`//`
26			`MOVS:`
27			`include "check_for_ints.v"
28			`else if (w && (si==16'hFFFF)) begin`
29			ir <= `NOP;
30			`int_num <= 8'd13;`
31			`state <= INT1;`
32			`end`
33			`else if ((repz\|repnz) & cxz)`
34			`state <= IFETCH;`
35			`else begin`
36			`if (!cyc_o) begin`
37			cyc_type <= `CT_RDMEM;
38			`lock_o <= w;`
39			`cyc_o <= 1'b1;`
40			`stb_o <= 1'b1;`
41			`we_o <= 1'b0;`
42			`adr_o <= dssi;`
43			`end`
44			`else if (ack_i) begin`
45			cyc_type <= `CT_PASSIVE;
46			`state <= w ? MOVS1 : MOVS3;`
47			`cyc_o <= 1'b0;`
48			`stb_o <= 1'b0;`
49			`a[7:0] <= dat_i;`
50			`si <= df ? si_dec : si_inc;`
51			`end`
52			`end`
53			`MOVS1:`
54			`if (!cyc_o) begin`
55			cyc_type <= `CT_WRMEM;
56			`cyc_o <= 1'b1;`
57			`stb_o <= 1'b1;`
58			`we_o <= 1'b1;`
59			`adr_o <= esdi;`
60			`dat_o <= a[7:0];`
61			`end`
62			`else if (ack_i) begin`
63			cyc_type <= `CT_PASSIVE;
64			`cyc_o <= 1'b0;`
65			`stb_o <= 1'b0;`
66			`we_o <= 1'b0;`
67			`di <= df ? di_dec : di_inc;`
68			`state <= MOVS2;`
69			`end`
70			`MOVS2:`
71			`begin`
72			cyc_type <= `CT_RDMEM;
73			`cyc_o <= 1'b1;`
74			`stb_o <= 1'b1;`
75			`we_o <= 1'b0;`
76			`adr_o <= dssi;`
77			`state <= MOVS3;`
78			`end`
79			`MOVS3:`
80			`if (ack_i) begin`
81			cyc_type <= `CT_PASSIVE;
82			`cyc_o <= 1'b0;`
83			`stb_o <= 1'b0;`
84			`a[7:0] <= dat_i;`
85			`si <= df ? si_dec : si_inc;`
86			`state <= MOVS4;`
87			`end`
88			`MOVS4:`
89			`begin`
90			cyc_type <= `CT_WRMEM;
91			`cyc_o <= 1'b1;`
92			`stb_o <= 1'b1;`
93			`we_o <= 1'b1;`
94			`adr_o <= esdi;`
95			`dat_o <= a[7:0];`
96			`state <= MOVS5;`
97			`end`
98			`MOVS5:`
99			`if (ack_i) begin`
100			cyc_type <= `CT_PASSIVE;
101			`lock_o <= 1'b0;`
102			`cyc_o <= 1'b0;`
103			`stb_o <= 1'b0;`
104			`we_o <= 1'b0;`
105			`di <= df ? di_dec : di_inc;`
106			`if (repz\|repnz) begin`
107			`cx <= cx_dec;`
108			`state <= MOVS;`
109			`end`
110			`else`
111			`state <= IFETCH;`
112			`end`

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[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [MOVS.v] - Blame information for rev 4