OpenCores
URL https://opencores.org/ocsvn/rtf8088/rtf8088/trunk

Subversion Repositories rtf8088

[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [NMI_DETECTOR.v] - Blame information for rev 4

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 robfinch
// ============================================================================
2
//  2009,2010  Robert Finch
3
//  rplaskitti[remove]@birdcomputer.ca
4
//  Stratford
5
//
6
//  
7
//  Detect an edge on nmi.
8
//
9
//
10
//  This source code is available for evaluation and validation purposes
11
//  only. This copyright statement and disclaimer must remain present in
12
//  the file.
13
//
14
//      NO WARRANTY.
15
//  THIS Work, IS PROVIDEDED "AS IS" WITH NO WARRANTIES OF ANY KIND, WHETHER
16
//  EXPRESS OR IMPLIED. The user must assume the entire risk of using the
17
//  Work.
18
//
19
//  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
20
//  INCIDENTAL, CONSEQUENTIAL, OR PUNITIVE DAMAGES WHATSOEVER RELATING TO
21
//  THE USE OF THIS WORK, OR YOUR RELATIONSHIP WITH THE AUTHOR.
22
//
23
//  IN ADDITION, IN NO EVENT DOES THE AUTHOR AUTHORIZE YOU TO USE THE WORK
24
//  IN APPLICATIONS OR SYSTEMS WHERE THE WORK'S FAILURE TO PERFORM CAN
25
//  REASONABLY BE EXPECTED TO RESULT IN A SIGNIFICANT PHYSICAL INJURY, OR IN
26
//  LOSS OF LIFE. ANY SUCH USE BY YOU IS ENTIRELY AT YOUR OWN RISK, AND YOU
27
//  AGREE TO HOLD THE AUTHOR AND CONTRIBUTORS HARMLESS FROM ANY CLAIMS OR
28
//  LOSSES RELATING TO SUCH UNAUTHORIZED USE.
29
//
30
//
31
//  Verilog 
32
//
33
// ============================================================================
34
//
35
module nmi_detector(RESET, CLK, nmi_i, rst_nmi, pe_nmi);
36
input RESET;
37
input CLK;
38
input nmi_i;
39
input rst_nmi;                          // reset the nmi flag
40
output pe_nmi;
41
reg pe_nmi;
42
 
43
reg prev_nmi;                           // records previous nmi state
44
 
45
always @(posedge CLK)
46
    if (RESET) begin
47
        prev_nmi <= 1'b0;
48
        pe_nmi <= 1'b0;
49
    end
50
    else begin
51
        prev_nmi <= nmi_i;
52
        if (nmi_i & !prev_nmi)
53
            pe_nmi <= 1'b1;
54
        else if (rst_nmi)
55
            pe_nmi <= 1'b0;
56
    end
57
 
58
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.