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[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [OUTW.v] - Blame information for rev 6

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//=============================================================================
//  OUTW
//  - output word data to IO.
//
//
//  2009,2010 Robert Finch
//  Stratford
//  robfinch<remove>@opencores.org
//
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//
//=============================================================================
//
OUTW:   // Entry point for OUT port,AX
        begin
                `INITIATE_CODE_READ
                state <= OUTW_NACK;
        end
OUTW_NACK:
        if (ack_i) begin
                `TERMINATE_CODE_READ
                ea <= {12'h000,dat_i};
                state <= OUTW1;
        end
OUTW1:  // Entry point for OUT [DX],AX
        begin
                cyc_type <= `CT_WRIO;
                lock_o <= 1'b1;
                mio_o <= 1'b0;
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                we_o  <= 1'b1;
                adr_o <= ea;
                dat_o <= al;
                state <= OUTW1_NACK;
        end
OUTW1_NACK:
        if (ack_i) begin
                cyc_type <= `CT_PASSIVE;
                stb_o <= 1'b0;
                we_o  <= 1'b0;
                state <= OUTW2;
        end
OUTW2:
        begin
                cyc_type <= `CT_WRIO;
                stb_o <= 1'b1;
                we_o  <= 1'b1;
                adr_o <= ea_inc;
                dat_o <= ah;
                state <= OUTW2_NACK;
        end
OUTW2_NACK:
        if (ack_i) begin
                cyc_type <= `CT_PASSIVE;
                lock_o <= 1'b0;
                mio_o <= 1'b1;
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                we_o  <= 1'b0;
                state <= IFETCH;
        end
 

Line No.	Rev	Author	Line
1	2	robfinch	`//=============================================================================`
2			`// OUTW`
3			`// - output word data to IO.`
4			`//`
5			`//`
6			`// 2009,2010 Robert Finch`
7			`// Stratford`
8			`// robfinch<remove>@opencores.org`
9			`//`
10			`//`
11			`// This source file is free software: you can redistribute it and/or modify`
12			`// it under the terms of the GNU Lesser General Public License as published`
13			`// by the Free Software Foundation, either version 3 of the License, or`
14			`// (at your option) any later version.`
15			`//`
16			`// This source file is distributed in the hope that it will be useful,`
17			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
18			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
19			`// GNU General Public License for more details.`
20			`//`
21			`// You should have received a copy of the GNU General Public License`
22			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
23			`//`
24			`//=============================================================================`
25			`//`
26			`OUTW: // Entry point for OUT port,AX`
27			`begin`
28			`INITIATE_CODE_READ
29			`state <= OUTW_NACK;`
30			`end`
31			`OUTW_NACK:`
32			`if (ack_i) begin`
33			`TERMINATE_CODE_READ
34			`ea <= {12'h000,dat_i};`
35			`state <= OUTW1;`
36			`end`
37			`OUTW1: // Entry point for OUT [DX],AX`
38			`begin`
39			cyc_type <= `CT_WRIO;
40			`lock_o <= 1'b1;`
41			`mio_o <= 1'b0;`
42			`cyc_o <= 1'b1;`
43			`stb_o <= 1'b1;`
44			`we_o <= 1'b1;`
45			`adr_o <= ea;`
46			`dat_o <= al;`
47			`state <= OUTW1_NACK;`
48			`end`
49			`OUTW1_NACK:`
50			`if (ack_i) begin`
51			cyc_type <= `CT_PASSIVE;
52			`stb_o <= 1'b0;`
53			`we_o <= 1'b0;`
54			`state <= OUTW2;`
55			`end`
56			`OUTW2:`
57			`begin`
58			cyc_type <= `CT_WRIO;
59			`stb_o <= 1'b1;`
60			`we_o <= 1'b1;`
61			`adr_o <= ea_inc;`
62			`dat_o <= ah;`
63			`state <= OUTW2_NACK;`
64			`end`
65			`OUTW2_NACK:`
66			`if (ack_i) begin`
67			cyc_type <= `CT_PASSIVE;
68			`lock_o <= 1'b0;`
69			`mio_o <= 1'b1;`
70			`cyc_o <= 1'b0;`
71			`stb_o <= 1'b0;`
72			`we_o <= 1'b0;`
73			`state <= IFETCH;`
74			`end`
75

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[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [OUTW.v] - Blame information for rev 6