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[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [POP.v] - Blame information for rev 4

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Line No. Rev Author Line
1 2 robfinch
// ============================================================================
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//  POP register from stack
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//
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//
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//  (C) 2009,2010  Robert Finch
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//  robfinch[remove]@opencores.org
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//  Stratford
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//
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//
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// This source file is free software: you can redistribute it and/or modify 
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// it under the terms of the GNU Lesser General Public License as published 
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// by the Free Software Foundation, either version 3 of the License, or     
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// (at your option) any later version.                                      
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//                                                                          
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// This source file is distributed in the hope that it will be useful,      
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// but WITHOUT ANY WARRANTY; without even the implied warranty of           
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
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// GNU General Public License for more details.                             
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//                                                                          
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// You should have received a copy of the GNU General Public License        
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
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//
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//
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//  Verilog 
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//
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// ============================================================================
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//
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POP:
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        begin
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                cyc_type <= `CT_RDMEM;
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                lock_o <= 1'b1;
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                cyc_o <= 1'b1;
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                stb_o <= 1'b1;
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                adr_o <= sssp;
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                w <= 1'b1;
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                rrr <= ir[2:0];
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                state <= POP1;
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        end
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POP1:
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        if (ack_i) begin
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                cyc_type <= `CT_PASSIVE;
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                stb_o <= 1'b0;
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                sp <= sp_inc;
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                res[7:0] <= dat_i;
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                case(ir)
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                `POP_SS: begin rrr <= 3'd2; end
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                `POP_ES: begin rrr <= 3'd0; end
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                `POP_DS: begin rrr <= 3'd3; end
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                `POPF:
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                        begin
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                                cf <= dat_i[0];
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                                pf <= dat_i[2];
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                                af <= dat_i[4];
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                                zf <= dat_i[6];
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                                sf <= dat_i[7];
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                        end
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                default: ;
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                endcase
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                state <= POP2;
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        end
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POP2:
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        begin
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                `CONTINUE_STACK_POP
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                state <= POP3;
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        end
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POP3:
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        if (ack_i) begin
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                state <= IFETCH;
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                cyc_type <= `CT_PASSIVE;
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                lock_o <= 1'b0;
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                cyc_o <= 1'b0;
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                stb_o <= 1'b0;
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                sp <= sp_inc;
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                res[15:8] <= dat_i;
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                case(ir)
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                `POP_AX,`POP_CX,`POP_BX,`POP_DX,
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                `POP_SI,`POP_DI,`POP_BP,`POP_SP:
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                        wrregs <= 1'b1;
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                `POP_SS,`POP_ES,`POP_DS:
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                        wrsregs <= 1'b1;
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                `POPF:
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                        begin
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                                tf <= dat_i[0];
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                                ie <= dat_i[1];
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                                df <= dat_i[2];
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                                vf <= dat_i[3];
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                        end
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                `POP_MEM:
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                        state <= STORE_DATA;
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                default: ;
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                endcase
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        end

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