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[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [PUSH.v] - Blame information for rev 4

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1 2 robfinch
// ============================================================================
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//  PUSH register to stack
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//
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//
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//  (C) 2009-2012  Robert Finch, Stratford
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//  robfinch[remove]@opencores.org
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//
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//
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// This source file is free software: you can redistribute it and/or modify 
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// it under the terms of the GNU Lesser General Public License as published 
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// by the Free Software Foundation, either version 3 of the License, or     
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// (at your option) any later version.                                      
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//                                                                          
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// This source file is distributed in the hope that it will be useful,      
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// but WITHOUT ANY WARRANTY; without even the implied warranty of           
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
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// GNU General Public License for more details.                             
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//                                                                          
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// You should have received a copy of the GNU General Public License        
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
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//
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//  Verilog 
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//
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// ============================================================================
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//
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PUSH:
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        begin
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                // Note SP is predecremented at the decode stage
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                cyc_type <= `CT_WRMEM;
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                lock_o <= 1'b1;
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                cyc_o <= 1'b1;
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                stb_o <= 1'b1;
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                we_o <= 1'b1;
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                adr_o <= sssp;
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                state <= PUSH1;
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                case(ir)
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                `PUSH_AX: dat_o <= ah;
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                `PUSH_BX: dat_o <= bh;
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                `PUSH_CX: dat_o <= ch;
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                `PUSH_DX: dat_o <= dh;
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                `PUSH_SP: dat_o <= sp[15:8];
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                `PUSH_BP: dat_o <= bp[15:8];
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                `PUSH_SI: dat_o <= si[15:8];
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                `PUSH_DI: dat_o <= di[15:8];
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                `PUSH_CS: dat_o <= cs[15:8];
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                `PUSH_DS: dat_o <= ds[15:8];
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                `PUSH_SS: dat_o <= ss[15:8];
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                `PUSH_ES: dat_o <= es[15:8];
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                `PUSHF:   dat_o <= flags[15:8];
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                8'hFF:  dat_o <= a[15:8];
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                default:        dat_o <= 8'hFF;         // only gets here if there's a hardware error
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                endcase
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        end
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PUSH1:
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        if (ack_i) begin
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                cyc_type <= `CT_PASSIVE;
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                sp <= sp_dec;
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                stb_o <= 1'b0;
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                we_o <= 1'b0;
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                state <= PUSH2;
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        end
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PUSH2:
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        begin
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                cyc_type <= `CT_WRMEM;
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                stb_o <= 1'b1;
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                we_o <= 1'b1;
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                adr_o <= sssp;
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                state <= PUSH3;
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                case(ir)
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                `PUSH_AX: dat_o <= al;
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                `PUSH_BX: dat_o <= bl;
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                `PUSH_CX: dat_o <= cl;
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                `PUSH_DX: dat_o <= dl;
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                `PUSH_SP: dat_o <= sp[7:0];
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                `PUSH_BP: dat_o <= bp[7:0];
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                `PUSH_SI: dat_o <= si[7:0];
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                `PUSH_DI: dat_o <= di[7:0];
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                `PUSH_CS: dat_o <= cs[7:0];
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                `PUSH_DS: dat_o <= ds[7:0];
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                `PUSH_SS: dat_o <= ss[7:0];
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                `PUSH_ES: dat_o <= es[7:0];
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                `PUSHF:   dat_o <= flags[7:0];
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                8'hFF: dat_o <= a[7:0];
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                default:        dat_o <= 8'hFF;         // only get's here if there's a hardware error
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                endcase
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        end
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// Note stack pointer is decrement already in DECODE
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//
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PUSH3:
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        if (ack_i) begin
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                cyc_type <= `CT_PASSIVE;
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                lock_o <= 1'b0;
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                cyc_o <= 1'b0;
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                stb_o <= 1'b0;
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                we_o <= 1'b0;
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                state <= IFETCH;
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        end

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