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[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [PUSH.v] - Blame information for rev 4

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// ============================================================================
//  PUSH register to stack
//
//
//  (C) 2009-2012  Robert Finch, Stratford
//  robfinch[remove]@opencores.org
//
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//
//  Verilog 
//
// ============================================================================
//
PUSH:
        begin
                // Note SP is predecremented at the decode stage
                cyc_type <= `CT_WRMEM;
                lock_o <= 1'b1;
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                we_o <= 1'b1;
                adr_o <= sssp;
                state <= PUSH1;
                case(ir)
                `PUSH_AX: dat_o <= ah;
                `PUSH_BX: dat_o <= bh;
                `PUSH_CX: dat_o <= ch;
                `PUSH_DX: dat_o <= dh;
                `PUSH_SP: dat_o <= sp[15:8];
                `PUSH_BP: dat_o <= bp[15:8];
                `PUSH_SI: dat_o <= si[15:8];
                `PUSH_DI: dat_o <= di[15:8];
                `PUSH_CS: dat_o <= cs[15:8];
                `PUSH_DS: dat_o <= ds[15:8];
                `PUSH_SS: dat_o <= ss[15:8];
                `PUSH_ES: dat_o <= es[15:8];
                `PUSHF:   dat_o <= flags[15:8];
                8'hFF:  dat_o <= a[15:8];
                default:        dat_o <= 8'hFF;         // only gets here if there's a hardware error
                endcase
        end
PUSH1:
        if (ack_i) begin
                cyc_type <= `CT_PASSIVE;
                sp <= sp_dec;
                stb_o <= 1'b0;
                we_o <= 1'b0;
                state <= PUSH2;
        end
PUSH2:
        begin
                cyc_type <= `CT_WRMEM;
                stb_o <= 1'b1;
                we_o <= 1'b1;
                adr_o <= sssp;
                state <= PUSH3;
                case(ir)
                `PUSH_AX: dat_o <= al;
                `PUSH_BX: dat_o <= bl;
                `PUSH_CX: dat_o <= cl;
                `PUSH_DX: dat_o <= dl;
                `PUSH_SP: dat_o <= sp[7:0];
                `PUSH_BP: dat_o <= bp[7:0];
                `PUSH_SI: dat_o <= si[7:0];
                `PUSH_DI: dat_o <= di[7:0];
                `PUSH_CS: dat_o <= cs[7:0];
                `PUSH_DS: dat_o <= ds[7:0];
                `PUSH_SS: dat_o <= ss[7:0];
                `PUSH_ES: dat_o <= es[7:0];
                `PUSHF:   dat_o <= flags[7:0];
                8'hFF: dat_o <= a[7:0];
                default:        dat_o <= 8'hFF;         // only get's here if there's a hardware error
                endcase
        end
 
// Note stack pointer is decrement already in DECODE
//
PUSH3:
        if (ack_i) begin
                cyc_type <= `CT_PASSIVE;
                lock_o <= 1'b0;
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                we_o <= 1'b0;
                state <= IFETCH;
        end

Line No.	Rev	Author	Line
1	2	robfinch	`// ============================================================================`
2			`// PUSH register to stack`
3			`//`
4			`//`
5			`// (C) 2009-2012 Robert Finch, Stratford`
6			`// robfinch[remove]@opencores.org`
7			`//`
8			`//`
9			`// This source file is free software: you can redistribute it and/or modify`
10			`// it under the terms of the GNU Lesser General Public License as published`
11			`// by the Free Software Foundation, either version 3 of the License, or`
12			`// (at your option) any later version.`
13			`//`
14			`// This source file is distributed in the hope that it will be useful,`
15			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
16			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
17			`// GNU General Public License for more details.`
18			`//`
19			`// You should have received a copy of the GNU General Public License`
20			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
21			`//`
22			`// Verilog`
23			`//`
24			`// ============================================================================`
25			`//`
26			`PUSH:`
27			`begin`
28			`// Note SP is predecremented at the decode stage`
29			cyc_type <= `CT_WRMEM;
30			`lock_o <= 1'b1;`
31			`cyc_o <= 1'b1;`
32			`stb_o <= 1'b1;`
33			`we_o <= 1'b1;`
34			`adr_o <= sssp;`
35			`state <= PUSH1;`
36			`case(ir)`
37			`PUSH_AX: dat_o <= ah;
38			`PUSH_BX: dat_o <= bh;
39			`PUSH_CX: dat_o <= ch;
40			`PUSH_DX: dat_o <= dh;
41			`PUSH_SP: dat_o <= sp[15:8];
42			`PUSH_BP: dat_o <= bp[15:8];
43			`PUSH_SI: dat_o <= si[15:8];
44			`PUSH_DI: dat_o <= di[15:8];
45			`PUSH_CS: dat_o <= cs[15:8];
46			`PUSH_DS: dat_o <= ds[15:8];
47			`PUSH_SS: dat_o <= ss[15:8];
48			`PUSH_ES: dat_o <= es[15:8];
49			`PUSHF: dat_o <= flags[15:8];
50			`8'hFF: dat_o <= a[15:8];`
51			`default: dat_o <= 8'hFF; // only gets here if there's a hardware error`
52			`endcase`
53			`end`
54			`PUSH1:`
55			`if (ack_i) begin`
56			cyc_type <= `CT_PASSIVE;
57			`sp <= sp_dec;`
58			`stb_o <= 1'b0;`
59			`we_o <= 1'b0;`
60			`state <= PUSH2;`
61			`end`
62			`PUSH2:`
63			`begin`
64			cyc_type <= `CT_WRMEM;
65			`stb_o <= 1'b1;`
66			`we_o <= 1'b1;`
67			`adr_o <= sssp;`
68			`state <= PUSH3;`
69			`case(ir)`
70			`PUSH_AX: dat_o <= al;
71			`PUSH_BX: dat_o <= bl;
72			`PUSH_CX: dat_o <= cl;
73			`PUSH_DX: dat_o <= dl;
74			`PUSH_SP: dat_o <= sp[7:0];
75			`PUSH_BP: dat_o <= bp[7:0];
76			`PUSH_SI: dat_o <= si[7:0];
77			`PUSH_DI: dat_o <= di[7:0];
78			`PUSH_CS: dat_o <= cs[7:0];
79			`PUSH_DS: dat_o <= ds[7:0];
80			`PUSH_SS: dat_o <= ss[7:0];
81			`PUSH_ES: dat_o <= es[7:0];
82			`PUSHF: dat_o <= flags[7:0];
83			`8'hFF: dat_o <= a[7:0];`
84			`default: dat_o <= 8'hFF; // only get's here if there's a hardware error`
85			`endcase`
86			`end`
87
88			`// Note stack pointer is decrement already in DECODE`
89			`//`
90			`PUSH3:`
91			`if (ack_i) begin`
92			cyc_type <= `CT_PASSIVE;
93			`lock_o <= 1'b0;`
94			`cyc_o <= 1'b0;`
95			`stb_o <= 1'b0;`
96			`we_o <= 1'b0;`
97			`state <= IFETCH;`
98			`end`

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[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [PUSH.v] - Blame information for rev 4