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[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [REGFILE.v] - Blame information for rev 4

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1 2 robfinch
//=============================================================================
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//  (C) 2009-2012 Robert Finch, Stratford
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//  robfinch<remove>@opencores.org
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//
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//  Register file
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//
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//
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// This source file is free software: you can redistribute it and/or modify 
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// it under the terms of the GNU Lesser General Public License as published 
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// by the Free Software Foundation, either version 3 of the License, or     
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// (at your option) any later version.                                      
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//                                                                          
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// This source file is distributed in the hope that it will be useful,      
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// but WITHOUT ANY WARRANTY; without even the implied warranty of           
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
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// GNU General Public License for more details.                             
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//                                                                          
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// You should have received a copy of the GNU General Public License        
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
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//
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//
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//=============================================================================
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//
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reg [15:0] rrro;
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reg [15:0] rmo;                          // register output (controlled by mod r/m byte)
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reg [15:0] rfso;
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reg pf;                                         // parity flag
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reg af;                                         // auxillary carry (half carry) flag
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reg zf, cf, vf;
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reg sf;                                         // sign flag
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reg df;                                         // direction flag
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reg ie;                                         // interrupt enable flag
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reg tf;
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wire [15:0] flags = {1'b0,1'b0,2'b00,vf,df,ie,tf,sf,zf,1'b0,af,1'b0,pf,1'b0,cf};
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reg [7:0] ir;                            // instruction register
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reg [7:0] ir2;                           // extended instruction register
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reg [15:0] ip;                           // instruction pointer
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reg [15:0] ir_ip;                        // instruction pointer of ir
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reg [15:0] ax;
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reg [15:0] bx;
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reg [15:0] cx;
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reg [15:0] dx;
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reg [15:0] si;                           // source index
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reg [15:0] di;                           // destination index
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reg [15:0] bp;                           // base pointer
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reg [15:0] sp;                           // stack pointer
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wire cxz = cx==16'h0000;        // CX is zero
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reg [15:0] cs;                           // code segment
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reg [15:0] ds;                           // data segment
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reg [15:0] es;                           // extra segment
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reg [15:0] ss;                           // stack segment
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// renamed byte registers for convenience
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wire [7:0] al = ax[7:0];
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wire [7:0] ah = ax[15:8];
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wire [7:0] dl = dx[7:0];
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wire [7:0] dh = dx[15:8];
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wire [7:0] cl = cx[7:0];
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wire [7:0] ch = cx[15:8];
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wire [7:0] bl = bx[7:0];
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wire [7:0] bh = bx[15:8];
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wire [19:0] csip = {cs,4'd0} + ip;
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wire [19:0] sssp = {ss,4'd0} + sp;
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wire [19:0] dssi = {ds,4'd0} + si;
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wire [19:0] esdi = {es,4'd0} + di;
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// Read port
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//
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always @(w or rrr or ax or bx or cx or dx or sp or bp or si or di)
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        case({w,rrr})
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        4'd0:   rrro <= {{8{ax[7]}},ax[7:0]};
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        4'd1:   rrro <= {{8{cx[7]}},cx[7:0]};
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        4'd2:   rrro <= {{8{dx[7]}},dx[7:0]};
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        4'd3:   rrro <= {{8{bx[7]}},bx[7:0]};
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        4'd4:   rrro <= {{8{ax[15]}},ax[15:8]};
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        4'd5:   rrro <= {{8{cx[15]}},cx[15:8]};
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        4'd6:   rrro <= {{8{dx[15]}},dx[15:8]};
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        4'd7:   rrro <= {{8{bx[15]}},bx[15:8]};
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        4'd8:   rrro <= ax;
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        4'd9:   rrro <= cx;
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        4'd10:  rrro <= dx;
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        4'd11:  rrro <= bx;
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        4'd12:  rrro <= sp;
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        4'd13:  rrro <= bp;
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        4'd14:  rrro <= si;
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        4'd15:  rrro <= di;
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        endcase
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// Second Read port
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//
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always @(w or rm or ax or bx or cx or dx or sp or bp or si or di)
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        case({w,rm})
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        4'd0:   rmo <= {{8{ax[7]}},ax[7:0]};
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        4'd1:   rmo <= {{8{cx[7]}},cx[7:0]};
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        4'd2:   rmo <= {{8{dx[7]}},dx[7:0]};
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        4'd3:   rmo <= {{8{bx[7]}},bx[7:0]};
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        4'd4:   rmo <= {{8{ax[15]}},ax[15:8]};
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        4'd5:   rmo <= {{8{cx[15]}},cx[15:8]};
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        4'd6:   rmo <= {{8{dx[15]}},dx[15:8]};
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        4'd7:   rmo <= {{8{bx[15]}},bx[15:8]};
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        4'd8:   rmo <= ax;
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        4'd9:   rmo <= cx;
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        4'd10:  rmo <= dx;
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        4'd11:  rmo <= bx;
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        4'd12:  rmo <= sp;
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        4'd13:  rmo <= bp;
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        4'd14:  rmo <= si;
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        4'd15:  rmo <= di;
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        endcase
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// Read segment registers
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//
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always @(sreg3 or es or cs or ds or ss)
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        case(sreg3)
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        3'd0:   rfso <= es;
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        3'd1:   rfso <= cs;
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        3'd2:   rfso <= ss;
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        3'd3:   rfso <= ds;
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        default:        rfso <= 16'h0000;
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        endcase

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