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[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [RETFPOP.v] - Blame information for rev 4

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// ============================================================================
//  RETFPOP: far return from subroutine and pop stack items
//  Fetch ip from stack
//
//
//  2009-2012  Robert Finch
//  robfinch[remove]@opencores.org
//  Stratford
//
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//
//  Verilog 
//
// ============================================================================
//
RETFPOP:
        begin
                lock_o <= 1'b1;
                `INITIATE_STACK_POP
                state <= RETFPOP1;
        end
RETFPOP1:
        if (ack_i) begin
                `PAUSE_STACK_POP
                ip[7:0] <= dat_i;
                state <= RETFPOP2;
        end
RETFPOP2:
        begin
                `CONTINUE_STACK_POP
                state <= RETFPOP3;
        end
RETFPOP3:
        if (ack_i) begin
                `PAUSE_STACK_POP
                ip[15:8] <= dat_i;
                state <= RETFPOP4;
        end
RETFPOP4:
        begin
                `CONTINUE_STACK_POP
                state <= RETFPOP5;
        end
RETFPOP5:
        if (ack_i) begin
                `PAUSE_STACK_POP
                cs[7:0] <= dat_i;
                state <= RETFPOP6;
        end
RETFPOP6:
        begin
                `CONTINUE_STACK_POP
                state <= RETFPOP7;
        end
RETFPOP7:
        if (ack_i) begin
                lock_o <= 1'b0;
                `COMPLETE_STACK_POP
                cs[15:8] <= dat_i;
                state <= RETFPOP8;
        end
RETFPOP8:
        begin
                wrregs <= 1'b1;
                w <= 1'b1;
                rrr <= 3'd4;
                res <= sp + data16;
                state <= IFETCH;
        end
 

Line No.	Rev	Author	Line
1	2	robfinch	`// ============================================================================`
2			`// RETFPOP: far return from subroutine and pop stack items`
3			`// Fetch ip from stack`
4			`//`
5			`//`
6			`// 2009-2012 Robert Finch`
7			`// robfinch[remove]@opencores.org`
8			`// Stratford`
9			`//`
10			`//`
11			`// This source file is free software: you can redistribute it and/or modify`
12			`// it under the terms of the GNU Lesser General Public License as published`
13			`// by the Free Software Foundation, either version 3 of the License, or`
14			`// (at your option) any later version.`
15			`//`
16			`// This source file is distributed in the hope that it will be useful,`
17			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
18			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
19			`// GNU General Public License for more details.`
20			`//`
21			`// You should have received a copy of the GNU General Public License`
22			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
23			`//`
24			`// Verilog`
25			`//`
26			`// ============================================================================`
27			`//`
28			`RETFPOP:`
29			`begin`
30			`lock_o <= 1'b1;`
31			`INITIATE_STACK_POP
32			`state <= RETFPOP1;`
33			`end`
34			`RETFPOP1:`
35			`if (ack_i) begin`
36			`PAUSE_STACK_POP
37			`ip[7:0] <= dat_i;`
38			`state <= RETFPOP2;`
39			`end`
40			`RETFPOP2:`
41			`begin`
42			`CONTINUE_STACK_POP
43			`state <= RETFPOP3;`
44			`end`
45			`RETFPOP3:`
46			`if (ack_i) begin`
47			`PAUSE_STACK_POP
48			`ip[15:8] <= dat_i;`
49			`state <= RETFPOP4;`
50			`end`
51			`RETFPOP4:`
52			`begin`
53			`CONTINUE_STACK_POP
54			`state <= RETFPOP5;`
55			`end`
56			`RETFPOP5:`
57			`if (ack_i) begin`
58			`PAUSE_STACK_POP
59			`cs[7:0] <= dat_i;`
60			`state <= RETFPOP6;`
61			`end`
62			`RETFPOP6:`
63			`begin`
64			`CONTINUE_STACK_POP
65			`state <= RETFPOP7;`
66			`end`
67			`RETFPOP7:`
68			`if (ack_i) begin`
69			`lock_o <= 1'b0;`
70			`COMPLETE_STACK_POP
71			`cs[15:8] <= dat_i;`
72			`state <= RETFPOP8;`
73			`end`
74			`RETFPOP8:`
75			`begin`
76			`wrregs <= 1'b1;`
77			`w <= 1'b1;`
78			`rrr <= 3'd4;`
79			`res <= sp + data16;`
80			`state <= IFETCH;`
81			`end`
82

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[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [RETFPOP.v] - Blame information for rev 4