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[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [SCASW.v] - Blame information for rev 4

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1 2 robfinch
// ============================================================================
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//  SCASW
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//
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//
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//  2009-2012  Robert Finch
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//  robfinch[remove]@opencores.org
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//  Stratford
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//
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//  
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// This source file is free software: you can redistribute it and/or modify 
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// it under the terms of the GNU Lesser General Public License as published 
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// by the Free Software Foundation, either version 3 of the License, or     
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// (at your option) any later version.                                      
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//                                                                          
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// This source file is distributed in the hope that it will be useful,      
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// but WITHOUT ANY WARRANTY; without even the implied warranty of           
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
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// GNU General Public License for more details.                             
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//                                                                          
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// You should have received a copy of the GNU General Public License        
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
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//
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//  Verilog 
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//
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// ============================================================================
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//
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SCASW:
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`include "check_for_ints.v"
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        else if (w && (di==16'hFFFF) && !df) begin
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                ir <= `NOP;
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                int_num <= 8'd13;
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                state <= INT1;
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        end
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        else if ((repz|repnz) & cxz)
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                state <= IFETCH;
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        else begin
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                if (!cyc_o) begin
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                        cyc_type <= `CT_RDMEM;
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                        lock_o <= 1'b1;
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                        cyc_o <= 1'b1;
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                        stb_o <= 1'b1;
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                        we_o  <= 1'b0;
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                        adr_o <= esdi;
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                end
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                else if (ack_i) begin
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                        cyc_type <= `CT_PASSIVE;
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                        state <= SCASW1;
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                        stb_o <= 1'b0;
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                        a <= ax;
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                        if (df) begin
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                                b[15:8] <= dat_i;
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                                di <= di_dec;
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                        end
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                        else begin
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                                b[7:0] <= dat_i;
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                                di <= di_inc;
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                        end
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                end
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        end
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SCASW1:
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        if (!stb_o) begin
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                cyc_type <= `CT_RDMEM;
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                stb_o <= 1'b1;
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                adr_o <= esdi;
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        end
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        else if (ack_i) begin
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                cyc_type <= `CT_PASSIVE;
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                state <= SCASW2;
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                lock_o <= 1'b0;
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                cyc_o <= 1'b0;
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                stb_o <= 1'b0;
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                we_o  <= 1'b0;
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                a <= ax;
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                if (df) begin
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                        b <= dat_i;
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                        di <= di_dec;
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                end
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                else begin
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                        b[15:8] <= dat_i;
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                        di <= di_inc;
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                end
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        end
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SCASW2:
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        begin
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                pf <= pres;
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                af <= carry   (1'b0,a[3],b[3],alu_o[3]);
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                cf <= carry   (1'b0,a[15],b[15],alu_o[15]);
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                vf <= overflow(1'b0,a[15],b[15],alu_o[15]);
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                sf <= resnw;
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                zf <= reszw;
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                if (repz|repnz)
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                        cx <= cx_dec;
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                if ((repz & reszw) | (repnz & !reszw))
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                        state <= SCASW;
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                else
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                        state <= IFETCH;
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        end

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