URL https://opencores.org/ocsvn/rtf8088/rtf8088/trunk

Subversion Repositories rtf8088

[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [SCASW.v] - Blame information for rev 6

Go to most recent revision | Details | Compare with Previous | View Log


// ============================================================================
//  SCASW
//
//
//  2009-2012  Robert Finch
//  robfinch[remove]@opencores.org
//  Stratford
//
//  
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//
//  Verilog 
//
// ============================================================================
//
SCASW:
`include "check_for_ints.v"
        else if (w && (di==16'hFFFF) && !df) begin
                ir <= `NOP;
                int_num <= 8'd13;
                state <= INT1;
        end
        else if ((repz|repnz) & cxz)
                state <= IFETCH;
        else begin
                if (!cyc_o) begin
                        cyc_type <= `CT_RDMEM;
                        lock_o <= 1'b1;
                        cyc_o <= 1'b1;
                        stb_o <= 1'b1;
                        we_o  <= 1'b0;
                        adr_o <= esdi;
                end
                else if (ack_i) begin
                        cyc_type <= `CT_PASSIVE;
                        state <= SCASW1;
                        stb_o <= 1'b0;
                        a <= ax;
                        if (df) begin
                                b[15:8] <= dat_i;
                                di <= di_dec;
                        end
                        else begin
                                b[7:0] <= dat_i;
                                di <= di_inc;
                        end
                end
        end
SCASW1:
        if (!stb_o) begin
                cyc_type <= `CT_RDMEM;
                stb_o <= 1'b1;
                adr_o <= esdi;
        end
        else if (ack_i) begin
                cyc_type <= `CT_PASSIVE;
                state <= SCASW2;
                lock_o <= 1'b0;
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                we_o  <= 1'b0;
                a <= ax;
                if (df) begin
                        b <= dat_i;
                        di <= di_dec;
                end
                else begin
                        b[15:8] <= dat_i;
                        di <= di_inc;
                end
        end
SCASW2:
        begin
                pf <= pres;
                af <= carry   (1'b0,a[3],b[3],alu_o[3]);
                cf <= carry   (1'b0,a[15],b[15],alu_o[15]);
                vf <= overflow(1'b0,a[15],b[15],alu_o[15]);
                sf <= resnw;
                zf <= reszw;
                if (repz|repnz)
                        cx <= cx_dec;
                if ((repz & reszw) | (repnz & !reszw))
                        state <= SCASW;
                else
                        state <= IFETCH;
        end

Line No.	Rev	Author	Line
1	2	robfinch	`// ============================================================================`
2			`// SCASW`
3			`//`
4			`//`
5			`// 2009-2012 Robert Finch`
6			`// robfinch[remove]@opencores.org`
7			`// Stratford`
8			`//`
9			`//`
10			`// This source file is free software: you can redistribute it and/or modify`
11			`// it under the terms of the GNU Lesser General Public License as published`
12			`// by the Free Software Foundation, either version 3 of the License, or`
13			`// (at your option) any later version.`
14			`//`
15			`// This source file is distributed in the hope that it will be useful,`
16			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
17			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
18			`// GNU General Public License for more details.`
19			`//`
20			`// You should have received a copy of the GNU General Public License`
21			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
22			`//`
23			`// Verilog`
24			`//`
25			`// ============================================================================`
26			`//`
27			`SCASW:`
28			`include "check_for_ints.v"
29			`else if (w && (di==16'hFFFF) && !df) begin`
30			ir <= `NOP;
31			`int_num <= 8'd13;`
32			`state <= INT1;`
33			`end`
34			`else if ((repz\|repnz) & cxz)`
35			`state <= IFETCH;`
36			`else begin`
37			`if (!cyc_o) begin`
38			cyc_type <= `CT_RDMEM;
39			`lock_o <= 1'b1;`
40			`cyc_o <= 1'b1;`
41			`stb_o <= 1'b1;`
42			`we_o <= 1'b0;`
43			`adr_o <= esdi;`
44			`end`
45			`else if (ack_i) begin`
46			cyc_type <= `CT_PASSIVE;
47			`state <= SCASW1;`
48			`stb_o <= 1'b0;`
49			`a <= ax;`
50			`if (df) begin`
51			`b[15:8] <= dat_i;`
52			`di <= di_dec;`
53			`end`
54			`else begin`
55			`b[7:0] <= dat_i;`
56			`di <= di_inc;`
57			`end`
58			`end`
59			`end`
60			`SCASW1:`
61			`if (!stb_o) begin`
62			cyc_type <= `CT_RDMEM;
63			`stb_o <= 1'b1;`
64			`adr_o <= esdi;`
65			`end`
66			`else if (ack_i) begin`
67			cyc_type <= `CT_PASSIVE;
68			`state <= SCASW2;`
69			`lock_o <= 1'b0;`
70			`cyc_o <= 1'b0;`
71			`stb_o <= 1'b0;`
72			`we_o <= 1'b0;`
73			`a <= ax;`
74			`if (df) begin`
75			`b <= dat_i;`
76			`di <= di_dec;`
77			`end`
78			`else begin`
79			`b[15:8] <= dat_i;`
80			`di <= di_inc;`
81			`end`
82			`end`
83			`SCASW2:`
84			`begin`
85			`pf <= pres;`
86			`af <= carry (1'b0,a[3],b[3],alu_o[3]);`
87			`cf <= carry (1'b0,a[15],b[15],alu_o[15]);`
88			`vf <= overflow(1'b0,a[15],b[15],alu_o[15]);`
89			`sf <= resnw;`
90			`zf <= reszw;`
91			`if (repz\|repnz)`
92			`cx <= cx_dec;`
93			`if ((repz & reszw) \| (repnz & !reszw))`
94			`state <= SCASW;`
95			`else`
96			`state <= IFETCH;`
97			`end`

Browse

Tools

Subversion Repositories rtf8088

[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [SCASW.v] - Blame information for rev 6