OpenCores
URL https://opencores.org/ocsvn/rtf8088/rtf8088/trunk

Subversion Repositories rtf8088

[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [STORE_DATA.v] - Blame information for rev 3

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 robfinch
// ============================================================================
2
//  STORE_DATA
3
//  - store data to memory.
4
//
5
//
6
//  (C) 2009,2010,2012  Robert Finch
7
//  robfinch[remove]@opencores.org
8
//
9
//
10
// This source file is free software: you can redistribute it and/or modify 
11
// it under the terms of the GNU Lesser General Public License as published 
12
// by the Free Software Foundation, either version 3 of the License, or     
13
// (at your option) any later version.                                      
14
//                                                                          
15
// This source file is distributed in the hope that it will be useful,      
16
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
17
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
18
// GNU General Public License for more details.                             
19
//                                                                          
20
// You should have received a copy of the GNU General Public License        
21
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
22
//
23
//
24
//  Verilog 
25
//
26
// ============================================================================
27
//
28
STORE_DATA:
29
        begin
30
                cyc_type <= `CT_WRMEM;
31
                lock_o <= bus_locked | w;
32
                cyc_o <= 1'b1;
33
                stb_o <= 1'b1;
34
                we_o  <= 1'b1;
35
                adr_o <= ea;
36
                dat_o <= res[7:0];
37
                state <= STORE_DATA1;
38
        end
39
STORE_DATA1:
40
        if (ack_i) begin
41
                cyc_type <= `CT_PASSIVE;
42
                stb_o <= 1'b0;
43
                we_o  <= 1'b0;
44
                if (w) begin
45
                        state <= STORE_DATA2;
46
                end
47
                else begin
48
                        cyc_o <= 1'b0;
49
                        lock_o <= 1'b0;
50
                        state <= IFETCH;
51
                end
52
        end
53
STORE_DATA2:
54
        begin
55
                cyc_type <= `CT_WRMEM;
56
                stb_o <= 1'b1;
57
                we_o  <= 1'b1;
58
                adr_o <= ea_inc;
59
                dat_o <= res[15:8];
60
                state <= STORE_DATA3;
61
        end
62
STORE_DATA3:
63
        if (ack_i) begin
64
                cyc_type <= `CT_PASSIVE;
65
                lock_o <= 1'b0;
66
                cyc_o <= 1'b0;
67
                stb_o <= 1'b0;
68
                we_o  <= 1'b0;
69
                state <= IFETCH;
70
        end

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.