OpenCores
URL https://opencores.org/ocsvn/rtf8088/rtf8088/trunk

Subversion Repositories rtf8088

[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [STOS.v] - Blame information for rev 4

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 robfinch
//=============================================================================
2
//  STOSB,STOSW
3
//  Store string data to memory.
4
//
5
//
6
//  2009-2012 Robert Finch
7
//  Stratford
8
//  robfinch<remove>@opencores.org
9
//
10
//
11
// This source file is free software: you can redistribute it and/or modify 
12
// it under the terms of the GNU Lesser General Public License as published 
13
// by the Free Software Foundation, either version 3 of the License, or     
14
// (at your option) any later version.                                      
15
//                                                                          
16
// This source file is distributed in the hope that it will be useful,      
17
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
18
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
19
// GNU General Public License for more details.                             
20
//                                                                          
21
// You should have received a copy of the GNU General Public License        
22
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
23
//
24
//=============================================================================
25
//
26
STOS:
27
`include "check_for_ints.v"
28
        else if (w && (di==16'hFFFF)) begin
29
                ir <= `NOP;
30
                int_num <= 8'd13;
31
                state <= INT1;
32
        end
33
        else if (repdone)
34
                state <= IFETCH;
35
        else begin
36
                if (!cyc_o) begin
37
                        cyc_type <= `CT_WRMEM;
38
                        lock_o <= w;
39
                        cyc_o <= 1'b1;
40
                        stb_o <= 1'b1;
41
                        we_o  <= 1'b1;
42
                        adr_o <= esdi;
43
                        dat_o <= (w & df) ? ah : al;
44
                end
45
                else if (ack_i) begin
46
                        cyc_type <= `CT_PASSIVE;
47
                        if (repz|repnz) begin
48
                                state <= w ? STOS1 : STOS;
49
                                cx <= cx_dec;
50
                        end
51
                        else
52
                                state <= w ? STOS1 : IFETCH;
53
                        lock_o <= w;
54
                        cyc_o <= w;
55
                        stb_o <= 1'b0;
56
                        we_o  <= 1'b0;
57
                        if (df)
58
                                di <= di_dec;
59
                        else
60
                                di <= di_inc;
61
                end
62
        end
63
STOS1:
64
        begin
65
                cyc_type <= `CT_WRMEM;
66
                cyc_o <= 1'b1;
67
                stb_o <= 1'b1;
68
                we_o  <= 1'b1;
69
                adr_o <= esdi;
70
                dat_o <= df ? al : ah;
71
                state <= STOS2;
72
        end
73
STOS2:
74
        if (ack_i) begin
75
                cyc_type <= `CT_PASSIVE;
76
                if (repz|repnz)
77
                        state <= STOS;
78
                else
79
                        state <= IFETCH;
80
                lock_o <= 1'b0;
81
                cyc_o <= 1'b0;
82
                stb_o <= 1'b0;
83
                we_o  <= 1'b0;
84
                if (df)
85
                        di <= di_dec;
86
                else
87
                        di <= di_inc;
88
        end

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.