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[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [WB8088_BRIDGE.v] - Blame information for rev 3

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Line No. Rev Author Line
1 2 robfinch
// ============================================================================
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//  8088 to WISHBONE bus bridge
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//
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//
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//  2009 Robert T Finch
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//  robfinch<remove>@opencores.org
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//
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//
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//  This source code is available for evaluation and validation purposes
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//  only. This copyright statement and disclaimer must remain present in
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//  the file.
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//
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//      NO WARRANTY.
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//  THIS Work, IS PROVIDEDED "AS IS" WITH NO WARRANTIES OF ANY KIND, WHETHER
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//  EXPRESS OR IMPLIED. The user must assume the entire risk of using the
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//  Work.
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//
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//  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
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//  INCIDENTAL, CONSEQUENTIAL, OR PUNITIVE DAMAGES WHATSOEVER RELATING TO
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//  THE USE OF THIS WORK, OR YOUR RELATIONSHIP WITH THE AUTHOR.
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//
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//  IN ADDITION, IN NO EVENT DOES THE AUTHOR AUTHORIZE YOU TO USE THE WORK
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//  IN APPLICATIONS OR SYSTEMS WHERE THE WORK'S FAILURE TO PERFORM CAN
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//  REASONABLY BE EXPECTED TO RESULT IN A SIGNIFICANT PHYSICAL INJURY, OR IN
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//  LOSS OF LIFE. ANY SUCH USE BY YOU IS ENTIRELY AT YOUR OWN RISK, AND YOU
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//  AGREE TO HOLD THE AUTHOR AND CONTRIBUTORS HARMLESS FROM ANY CLAIMS OR
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//  LOSSES RELATING TO SUCH UNAUTHORIZED USE.
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//
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//
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//  Verilog 
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//
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//  Connects an internal WISHBONE bus to the regular 8088 bus.
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//  If there is a hold acknowledge, a number of line have to be tri-stated.
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//
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//  Slice 16 / LUTs 30 / FF's 5 / 307.977 MHz
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// ============================================================================
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//
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`ifndef CT_INTA
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`include "cycle_types.v"
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`endif
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module wb8088_bridge(
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rst_i, clk_i,
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nmi_i, irq_i, busy_i, inta_o,
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stb_o, ack_i, we_o, adr_o, dat_i, dat_o,
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ie, cyc_type, S43,
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RESET, CLK, NMI, INTR, INTA_n, ALE, DEN_n, DT_R, IO_M, RD_n, WR_n, READY, A, AD, SSO,
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TEST_n, HOLD, HLDA
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);
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parameter T0 = 3'd0;
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parameter T1 = 3'd1;
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parameter T2 = 3'd2;
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parameter T3 = 3'd3;
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parameter T4 = 3'd4;
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output rst_i;
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output clk_i;
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output nmi_i;
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output irq_i;
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output busy_i;
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input inta_o;
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input stb_o;
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output ack_i;
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input we_o;
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input [19:0] adr_o;
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input [7:0] dat_o;
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output [7:0] dat_i;
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input ie;
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input [2:0] cyc_type;
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input [1:0] S43;
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input RESET;
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input CLK;
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input NMI;
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input INTR;
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output INTA_n;
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output ALE;
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output DEN_n;
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output DT_R;
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output IO_M;
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output RD_n;
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output WR_n;
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input READY;
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output [19:8] A;
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tri [19:8] A;
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inout [7:0] AD;
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tri [7:0] AD;
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output SSO;
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input TEST_n;
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input HOLD;
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output HLDA;
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reg HLDA;
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reg [2:0] Tcyc;                          // "T" cycle
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wire IsT1 = Tcyc==T1;
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wire IsT2 = Tcyc==T2;
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wire IsT3 = Tcyc==T3;
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wire IsT4 = Tcyc==T4;
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wire IsT23 = (Tcyc==T2) || (Tcyc==T3);
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assign rst_i = RESET;
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assign clk_i = CLK;
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assign irq_i = INTR;
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assign nmi_i = NMI;
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assign busy_i = TEST_n;
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// Will not get to T4 unless READY is active
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assign ack_i = IsT3 & READY;
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assign ALE = IsT1 && !CLK;      // high pulse during clock low
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assign RD_n = HLDA ? 1'bz : !(stb_o && !we_o && IsT23);
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assign WR_n = HLDA ? 1'bz : !(stb_o &&  we_o && IsT23);
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assign INTA_n = !(inta_o & IsT23);
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assign dat_i = AD[7:0];
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assign AD[7:0] = HLDA ? 8'bz : IsT1 ? (inta_o ? 8'bz : adr_o[7:0]) :      // address cycle
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                                                           (we_o ? dat_o : 8'bz);               // data cycle
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assign A[15:8] = (HLDA | inta_o) ? 8'bz : adr_o[15:8];
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assign A[19:16] = HLDA ? 4'bz : IsT1 ? adr_o[19:16] : {1'b0,ie,S43};
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assign DEN_n = HLDA ? 1'bz : !(we_o ? IsT23 || (IsT4 && !CLK) :
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                                  (CLK && IsT2) || IsT3 || (IsT4 && !CLK));
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assign DT_R = HLDA ? 1'bz : we_o;
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assign IO_M = cyc_type==`CT_RDIO || cyc_type==`CT_WRIO || cyc_type==`CT_HALT || cyc_type==`CT_INTA;
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assign SSO = cyc_type==`CT_RDIO || cyc_type==`CT_HALT || cyc_type==`CT_RDMEM || cyc_type==`CT_PASSIVE;
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// T State generator
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// Tcyc:
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// - bus cycle state machine
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// The machine sits in state T0 until a bus request is present, then transitions to state T1.
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// The machine sits in state T1 if there is a HOLD present
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// State T2 always moves to state T3
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// The machine sits in state T3 until the bus transfer is acknowledged
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// State T4 waits for the WISHBONE bus to acknowledge bus cycle completion.
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always @(negedge CLK)
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        if (RESET)
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                Tcyc <= T4;
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        else begin
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                case(Tcyc)
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                T0: if (stb_o) Tcyc <= T1;      // If there is a request for a bus cycle
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                T1: Tcyc <= HOLD ? T1 : T2;     // HOLD in the T1 state
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                T2: Tcyc <= T3;                         // always move to next
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                T3:     if (READY) Tcyc <= T4;  // wait for READY signal
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                T4:     if (!stb_o) Tcyc <= T0; // wait for end of bus cycle
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                default: Tcyc <= T4;
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                endcase
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        end
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// HOLD generator
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// - drive HLDA low as soon as HOLD goes low
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// - drive HLDA active if there is a HOLD during T1 or T4
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//
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always @(negedge CLK)
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        if (RESET)
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                HLDA <= 1'b0;
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        else begin
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                if (HOLD) begin
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                        if (Tcyc==T1) HLDA <= 1'b1;
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                        if (Tcyc==T4) HLDA <= 1'b1;
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                end
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                else
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                        HLDA <= 1'b0;
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        end
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endmodule
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