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[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [WRITE_BACK.v] - Blame information for rev 7

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Line No. Rev Author Line
1 2 robfinch
//=============================================================================
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//  2009,2010,2012 Robert Finch
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//  Stratford
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//  robfinch<remove>@opencores.org
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//
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//  WRITE_BACK state
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//  - update the register file
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//
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//
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// This source file is free software: you can redistribute it and/or modify 
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// it under the terms of the GNU Lesser General Public License as published 
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// by the Free Software Foundation, either version 3 of the License, or     
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// (at your option) any later version.                                      
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//                                                                          
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// This source file is distributed in the hope that it will be useful,      
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// but WITHOUT ANY WARRANTY; without even the implied warranty of           
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
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// GNU General Public License for more details.                             
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//                                                                          
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// You should have received a copy of the GNU General Public License        
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
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//
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//=============================================================================
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//
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if (wrregs)
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        case({w,rrr})
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        4'b0000:        ax[7:0] <= res[7:0];
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        4'b0001:        cx[7:0] <= res[7:0];
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        4'b0010:        dx[7:0] <= res[7:0];
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        4'b0011:        bx[7:0] <= res[7:0];
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        4'b0100:        ax[15:8] <= res[7:0];
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        4'b0101:        cx[15:8] <= res[7:0];
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        4'b0110:        dx[15:8] <= res[7:0];
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        4'b0111:        bx[15:8] <= res[7:0];
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        4'b1000:        ax <= res;
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        4'b1001:        cx <= res;
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        4'b1010:        dx <= res;
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        4'b1011:        bx <= res;
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        4'b1100:        sp <= res;
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        4'b1101:        bp <= res;
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        4'b1110:        si <= res;
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        4'b1111:        di <= res;
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        endcase
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// Write to segment register
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//
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if (wrsregs)
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        case(rrr)
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        3'd0:   es <= res;
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        3'd1:   cs <= res;
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        3'd2:   ss <= res;
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        3'd3:   ds <= res;
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        default:        ;
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        endcase

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