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[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [WRITE_SEG.v] - Blame information for rev 3

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//=============================================================================
//  2009,2010 Robert Finch
//  Stratford
//  eq<remove>@birdcomputer.ca
//
//  WRITE_SEG state
//  - update the segment register
//
//
//      NO WARRANTY.
//  THIS Work, IS PROVIDEDED "AS IS" WITH NO WARRANTIES OF ANY KIND, WHETHER
//      EXPRESS OR IMPLIED. The user must assume the entire risk of using the
//      Work.
//
//      IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
//  INCIDENTAL, CONSEQUENTIAL, OR PUNITIVE DAMAGES WHATSOEVER RELATING TO
//  THE USE OF THIS WORK, OR YOUR RELATIONSHIP WITH THE AUTHOR.
//
//      IN ADDITION, IN NO EVENT DOES THE AUTHOR AUTHORIZE YOU TO USE THE WORK
//      IN APPLICATIONS OR SYSTEMS WHERE THE WORK'S FAILURE TO PERFORM CAN
//      REASONABLY BE EXPECTED TO RESULT IN A SIGNIFICANT PHYSICAL INJURY, OR IN
//      LOSS OF LIFE. ANY SUCH USE BY YOU IS ENTIRELY AT YOUR OWN RISK, AND YOU
//      AGREE TO HOLD THE AUTHOR AND CONTRIBUTORS HARMLESS FROM ANY CLAIMS OR
//      LOSSES RELATING TO SUCH UNAUTHORIZED USE.
//
//=============================================================================
//
// Write to segment register
//
WRITE_SEG:
        begin
                state <= IFETCH;
                case(rrr)
                3'd0:   es <= res;
                3'd1:   cs <= res;
                3'd2:   ss <= res;
                3'd3:   ds <= res;
                default:        ;
                endcase
        end

Line No.	Rev	Author	Line
1	2	robfinch	`//=============================================================================`
2			`// 2009,2010 Robert Finch`
3			`// Stratford`
4			`// eq<remove>@birdcomputer.ca`
5			`//`
6			`// WRITE_SEG state`
7			`// - update the segment register`
8			`//`
9			`//`
10			`// NO WARRANTY.`
11			`// THIS Work, IS PROVIDEDED "AS IS" WITH NO WARRANTIES OF ANY KIND, WHETHER`
12			`// EXPRESS OR IMPLIED. The user must assume the entire risk of using the`
13			`// Work.`
14			`//`
15			`// IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY`
16			`// INCIDENTAL, CONSEQUENTIAL, OR PUNITIVE DAMAGES WHATSOEVER RELATING TO`
17			`// THE USE OF THIS WORK, OR YOUR RELATIONSHIP WITH THE AUTHOR.`
18			`//`
19			`// IN ADDITION, IN NO EVENT DOES THE AUTHOR AUTHORIZE YOU TO USE THE WORK`
20			`// IN APPLICATIONS OR SYSTEMS WHERE THE WORK'S FAILURE TO PERFORM CAN`
21			`// REASONABLY BE EXPECTED TO RESULT IN A SIGNIFICANT PHYSICAL INJURY, OR IN`
22			`// LOSS OF LIFE. ANY SUCH USE BY YOU IS ENTIRELY AT YOUR OWN RISK, AND YOU`
23			`// AGREE TO HOLD THE AUTHOR AND CONTRIBUTORS HARMLESS FROM ANY CLAIMS OR`
24			`// LOSSES RELATING TO SUCH UNAUTHORIZED USE.`
25			`//`
26			`//=============================================================================`
27			`//`
28			`// Write to segment register`
29			`//`
30			`WRITE_SEG:`
31			`begin`
32			`state <= IFETCH;`
33			`case(rrr)`
34			`3'd0: es <= res;`
35			`3'd1: cs <= res;`
36			`3'd2: ss <= res;`
37			`3'd3: ds <= res;`
38			`default: ;`
39			`endcase`
40			`end`

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[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [WRITE_SEG.v] - Blame information for rev 3