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[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [rtf8088sys.v] - Blame information for rev 4

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Line No. Rev Author Line
1 2 robfinch
 
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module rtf8088sys();
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reg rst;
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reg sys_clk;
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wire cpu_mio;
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wire cpu_cyc;
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wire cpu_stb;
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wire cpu_ack;
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wire cpu_we;
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wire [19:0] cpu_adr;
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wire [7:0] cpu_dato;
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reg [7:0] cpu_dati;
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wire stkmem_ack;
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wire [7:0] stkmem_o;
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wire [7:0] bootromo;
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wire br_acko;
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wire mem_ack;
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wire [7:0] memo;
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initial begin
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        rst = 1'b0;
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        sys_clk = 1'b0;
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        #100 rst = 1'b1;
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        #100 rst = 1'b0;
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end
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always #10 sys_clk = ~sys_clk;
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reg [7:0] mem [0:65535];
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wire csmem = cpu_cyc && cpu_stb && cpu_adr[19:16]==4'h0;
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always @(posedge sys_clk)
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        if (csmem & cpu_we) begin
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                $display("wrote mem[%h]=%h", cpu_adr,cpu_dato);
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                mem[cpu_adr[15:0]] <= cpu_dato;
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        end
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assign mem_ack = csmem;
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assign memo = csmem ? mem[cpu_adr[15:0]] : 8'h00;
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bootrom u3
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(
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        .cyc(cpu_cyc),
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        .stb(cpu_stb),
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        .adr(cpu_adr),
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        .o(bootromo),
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        .acko(br_acko)
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);
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stkmem u2
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(
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        .clk_i(sys_clk),
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        .cyc_i(cpu_cyc),
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        .stb_i(cpu_stb),
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        .ack_o(stkmem_ack),
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        .we_i(cpu_we),
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        .adr_i(cpu_adr),
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        .dat_i(cpu_dato),
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        .dat_o(stkmem_o)
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);
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always @(stkmem_o or bootromo or memo)
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        cpu_dati = stkmem_o|bootromo|memo;
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assign cpu_ack = stkmem_ack|br_acko|mem_ack;
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rtf8088 u1
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(
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        .rst_i(rst),
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        .clk_i(sys_clk),
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        .nmi_i(1'b0),
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        .irq_i(1'b0),
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        .busy_i(1'b0),
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        .inta_o(),
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        .lock_o(),
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        .mio_o(cpu_mio),
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        .cyc_o(cpu_cyc),
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        .stb_o(cpu_stb),
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        .ack_i(cpu_ack),
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        .we_o(cpu_we),
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        .adr_o(cpu_adr),
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        .dat_o(cpu_dato),
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        .dat_i(cpu_dati)
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);
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endmodule
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module stkmem(clk_i, cyc_i, stb_i, ack_o, we_i, adr_i, dat_i, dat_o);
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input clk_i;
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input cyc_i;
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input stb_i;
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output ack_o;
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input we_i;
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input [19:0] adr_i;
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input [7:0] dat_i;
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output [7:0] dat_o;
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reg [10:0] rra;
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reg [7:0] mem [2047:0];
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wire cs = cyc_i && stb_i && adr_i[19:11]==9'h003;
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assign ack_o = cs;
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always @(negedge clk_i)
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        rra <= adr_i[10:0];
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always @(negedge clk_i)
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        if (cs & we_i)
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                mem[adr_i[10:0]] <= dat_i;
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assign dat_o = cs ? mem[rra] : 8'h00;
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endmodule

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