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robfinch |
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// Determine segment register for memory access.
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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//
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always @(modrm or prefix1 or prefix2 or cs or ds or es or ss or ir)
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case(ir)
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`SCASB: seg_reg <= es;
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`SCASW: seg_reg <= es;
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default:
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case(prefix1)
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`CS: seg_reg <= cs;
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`DS: seg_reg <= ds;
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`ES: seg_reg <= es;
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`SS: seg_reg <= ss;
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default:
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case(prefix2)
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`CS: seg_reg <= cs;
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`DS: seg_reg <= ds;
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`ES: seg_reg <= es;
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`SS: seg_reg <= ss;
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default:
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casex(ir)
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`CMPSB: seg_reg <= ds;
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`CMPSW: seg_reg <= ds;
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`LODSB: seg_reg <= ds;
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`LODSW: seg_reg <= ds;
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`MOVSB: seg_reg <= ds;
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`MOVSW: seg_reg <= ds;
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`STOSB: seg_reg <= ds;
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`STOSW: seg_reg <= ds;
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`MOV_AL2M: seg_reg <= ds;
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`MOV_AX2M: seg_reg <= ds;
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default:
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case(modrm)
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5'b00_000: seg_reg <= ds;
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5'b00_001: seg_reg <= ds;
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5'b00_010: seg_reg <= ss;
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5'b00_011: seg_reg <= ss;
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5'b00_100: seg_reg <= ds;
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5'b00_101: seg_reg <= ds;
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5'b00_110: seg_reg <= ds;
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5'b00_111: seg_reg <= ds;
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5'b01_000: seg_reg <= ds;
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5'b01_001: seg_reg <= ds;
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5'b01_010: seg_reg <= ss;
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5'b01_011: seg_reg <= ss;
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5'b01_100: seg_reg <= ds;
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5'b01_101: seg_reg <= ds;
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5'b01_110: seg_reg <= ss;
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5'b01_111: seg_reg <= ds;
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5'b10_000: seg_reg <= ds;
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5'b10_001: seg_reg <= ds;
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5'b10_010: seg_reg <= ss;
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5'b10_011: seg_reg <= ss;
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5'b10_100: seg_reg <= ds;
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5'b10_101: seg_reg <= ds;
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5'b10_110: seg_reg <= ss;
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5'b10_111: seg_reg <= ds;
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default: seg_reg <= ds;
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endcase
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endcase
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endcase
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endcase
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endcase
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always @(state or modrm or prefix1 or prefix2 or ir)
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case(state)
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IFETCH,XI_FETCH,DECODE,FETCH_IMM8,FETCH_IMM16,FETCH_DISP8:
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S43 <= 2'b10; // code segment
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PUSH,PUSH1,POP,POP1,
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IRET,IRET1,IRET2,IRET3,IRET4,IRET5,
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RETFPOP,RETFPOP1,RETFPOP2,RETFPOP3,
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RETPOP,RETPOP1:
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S43 <= 2'b01; // stack
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default:
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case(prefix1)
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`CS: S43 <= 2'b10;
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`DS: S43 <= 2'b11;
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`ES: S43 <= 2'b00;
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`SS: S43 <= 2'b01;
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default:
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case(prefix2)
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`CS: S43 <= 2'b10;
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`DS: S43 <= 2'b11;
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`ES: S43 <= 2'b00;
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`SS: S43 <= 2'b01;
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default:
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casex(ir)
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`CMPSB: S43 <= 2'b11;
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`CMPSW: S43 <= 2'b11;
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`LODSB: S43 <= 2'b11;
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`LODSW: S43 <= 2'b11;
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`MOVSB: S43 <= 2'b11;
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`MOVSW: S43 <= 2'b11;
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`STOSB: S43 <= 2'b11;
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`STOSW: S43 <= 2'b11;
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`MOV_AL2M: S43 <= 2'b11;
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`MOV_AX2M: S43 <= 2'b11;
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default:
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case(modrm)
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5'b00_000: S43 <= 2'b11;
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5'b00_001: S43 <= 2'b11;
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5'b00_010: S43 <= 2'b01;
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5'b00_011: S43 <= 2'b01;
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5'b00_100: S43 <= 2'b11;
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5'b00_101: S43 <= 2'b11;
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5'b00_110: S43 <= 2'b11;
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5'b00_111: S43 <= 2'b11;
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5'b01_000: S43 <= 2'b11;
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5'b01_001: S43 <= 2'b11;
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5'b01_010: S43 <= 2'b01;
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5'b01_011: S43 <= 2'b01;
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5'b01_100: S43 <= 2'b11;
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5'b01_101: S43 <= 2'b11;
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5'b01_110: S43 <= 2'b01;
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5'b01_111: S43 <= 2'b11;
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5'b10_000: S43 <= 2'b11;
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5'b10_001: S43 <= 2'b11;
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5'b10_010: S43 <= 2'b01;
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5'b10_011: S43 <= 2'b01;
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5'b10_100: S43 <= 2'b11;
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5'b10_101: S43 <= 2'b11;
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5'b10_110: S43 <= 2'b01;
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5'b10_111: S43 <= 2'b11;
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default: S43 <= 2'b11;
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endcase // modrm
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endcase // ir
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endcase // prefix2
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endcase // prefix1
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endcase // state
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