OpenCores
URL https://opencores.org/ocsvn/rtf8088/rtf8088/trunk

Subversion Repositories rtf8088

[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [which_seg.v] - Blame information for rev 3

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 robfinch
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
2
// Determine segment register for memory access.
3
//
4
// This source file is free software: you can redistribute it and/or modify 
5
// it under the terms of the GNU Lesser General Public License as published 
6
// by the Free Software Foundation, either version 3 of the License, or     
7
// (at your option) any later version.                                      
8
//                                                                          
9
// This source file is distributed in the hope that it will be useful,      
10
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
11
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
12
// GNU General Public License for more details.                             
13
//                                                                          
14
// You should have received a copy of the GNU General Public License        
15
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
16
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
17
//
18
always @(modrm or prefix1 or prefix2 or cs or ds or es or ss or ir)
19
        case(ir)
20
        `SCASB: seg_reg <= es;
21
        `SCASW: seg_reg <= es;
22
        default:
23
                case(prefix1)
24
                `CS: seg_reg <= cs;
25
                `DS: seg_reg <= ds;
26
                `ES: seg_reg <= es;
27
                `SS: seg_reg <= ss;
28
                default:
29
                        case(prefix2)
30
                        `CS: seg_reg <= cs;
31
                        `DS: seg_reg <= ds;
32
                        `ES: seg_reg <= es;
33
                        `SS: seg_reg <= ss;
34
                        default:
35
                                casex(ir)
36
                                `CMPSB: seg_reg <= ds;
37
                                `CMPSW: seg_reg <= ds;
38
                                `LODSB: seg_reg <= ds;
39
                                `LODSW: seg_reg <= ds;
40
                                `MOVSB: seg_reg <= ds;
41
                                `MOVSW: seg_reg <= ds;
42
                                `STOSB: seg_reg <= ds;
43
                                `STOSW: seg_reg <= ds;
44
                                `MOV_AL2M: seg_reg <= ds;
45
                                `MOV_AX2M: seg_reg <= ds;
46
                                default:
47
                                        case(modrm)
48
                                        5'b00_000:      seg_reg <= ds;
49
                                        5'b00_001:      seg_reg <= ds;
50
                                        5'b00_010:      seg_reg <= ss;
51
                                        5'b00_011:      seg_reg <= ss;
52
                                        5'b00_100:      seg_reg <= ds;
53
                                        5'b00_101:      seg_reg <= ds;
54
                                        5'b00_110:      seg_reg <= ds;
55
                                        5'b00_111:      seg_reg <= ds;
56
 
57
                                        5'b01_000:      seg_reg <= ds;
58
                                        5'b01_001:      seg_reg <= ds;
59
                                        5'b01_010:      seg_reg <= ss;
60
                                        5'b01_011:      seg_reg <= ss;
61
                                        5'b01_100:      seg_reg <= ds;
62
                                        5'b01_101:      seg_reg <= ds;
63
                                        5'b01_110:      seg_reg <= ss;
64
                                        5'b01_111:      seg_reg <= ds;
65
 
66
                                        5'b10_000:      seg_reg <= ds;
67
                                        5'b10_001:      seg_reg <= ds;
68
                                        5'b10_010:      seg_reg <= ss;
69
                                        5'b10_011:      seg_reg <= ss;
70
                                        5'b10_100:      seg_reg <= ds;
71
                                        5'b10_101:      seg_reg <= ds;
72
                                        5'b10_110:      seg_reg <= ss;
73
                                        5'b10_111:      seg_reg <= ds;
74
 
75
                                        default:        seg_reg <= ds;
76
                                        endcase
77
                                endcase
78
                        endcase
79
                endcase
80
        endcase
81
 
82
        always @(state or modrm or prefix1 or prefix2 or ir)
83
                case(state)
84
                IFETCH,XI_FETCH,DECODE,FETCH_IMM8,FETCH_IMM16,FETCH_DISP8:
85
                        S43 <= 2'b10;   // code segment
86
                PUSH,PUSH1,POP,POP1,
87
                IRET,IRET1,IRET2,IRET3,IRET4,IRET5,
88
                RETFPOP,RETFPOP1,RETFPOP2,RETFPOP3,
89
                RETPOP,RETPOP1:
90
                        S43 <= 2'b01;   // stack
91
                default:
92
                        case(prefix1)
93
                        `CS: S43 <= 2'b10;
94
                        `DS: S43 <= 2'b11;
95
                        `ES: S43 <= 2'b00;
96
                        `SS: S43 <= 2'b01;
97
                        default:
98
                                case(prefix2)
99
                                `CS: S43 <= 2'b10;
100
                                `DS: S43 <= 2'b11;
101
                                `ES: S43 <= 2'b00;
102
                                `SS: S43 <= 2'b01;
103
                                default:
104
                                        casex(ir)
105
                                        `CMPSB: S43 <= 2'b11;
106
                                        `CMPSW: S43 <= 2'b11;
107
                                        `LODSB: S43 <= 2'b11;
108
                                        `LODSW: S43 <= 2'b11;
109
                                        `MOVSB: S43 <= 2'b11;
110
                                        `MOVSW: S43 <= 2'b11;
111
                                        `STOSB: S43 <= 2'b11;
112
                                        `STOSW: S43 <= 2'b11;
113
                                        `MOV_AL2M: S43 <= 2'b11;
114
                                        `MOV_AX2M: S43 <= 2'b11;
115
                                        default:
116
                                                case(modrm)
117
                                                5'b00_000:      S43 <= 2'b11;
118
                                                5'b00_001:      S43 <= 2'b11;
119
                                                5'b00_010:      S43 <= 2'b01;
120
                                                5'b00_011:      S43 <= 2'b01;
121
                                                5'b00_100:      S43 <= 2'b11;
122
                                                5'b00_101:      S43 <= 2'b11;
123
                                                5'b00_110:      S43 <= 2'b11;
124
                                                5'b00_111:      S43 <= 2'b11;
125
 
126
                                                5'b01_000:      S43 <= 2'b11;
127
                                                5'b01_001:      S43 <= 2'b11;
128
                                                5'b01_010:      S43 <= 2'b01;
129
                                                5'b01_011:      S43 <= 2'b01;
130
                                                5'b01_100:      S43 <= 2'b11;
131
                                                5'b01_101:      S43 <= 2'b11;
132
                                                5'b01_110:      S43 <= 2'b01;
133
                                                5'b01_111:      S43 <= 2'b11;
134
 
135
                                                5'b10_000:      S43 <= 2'b11;
136
                                                5'b10_001:      S43 <= 2'b11;
137
                                                5'b10_010:      S43 <= 2'b01;
138
                                                5'b10_011:      S43 <= 2'b01;
139
                                                5'b10_100:      S43 <= 2'b11;
140
                                                5'b10_101:      S43 <= 2'b11;
141
                                                5'b10_110:      S43 <= 2'b01;
142
                                                5'b10_111:      S43 <= 2'b11;
143
 
144
                                                default:        S43 <= 2'b11;
145
                                                endcase // modrm
146
                                        endcase // ir
147
                                endcase // prefix2
148
                        endcase // prefix1
149
                endcase // state
150
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.