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robfinch |
`timescale 1ns/1ps
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// ============================================================================
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// __
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// \\__/ o\ (C) 2013-2023 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \/_// robfinch@finitron.ca
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// ||
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//
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//
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// BSD 3-Clause License
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice, this
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// list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// ============================================================================
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import fta_bus_pkg::*;
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module fta_asynch2sync128(rst, clk, req_i, resp_o, req_o, resp_i);
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input rst;
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input clk;
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input fta_cmd_request128_t req_i;
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output fta_cmd_response128_t resp_o;
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output fta_cmd_request128_t req_o;
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input fta_cmd_response128_t resp_i;
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reg aer_i;
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always_ff @(posedge clk, posedge rst)
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if (rst) begin
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req_o <= 'd0;
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resp_o <= 'd0;
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end
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else begin
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aer_i <= resp_i.ack|resp_i.err|resp_i.rty;
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// If a cycle is pulsed, latch the request.
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if (req_i.cyc)
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req_o <= req_i;
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// On an ack, clear the request
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else if (resp_i.ack|resp_i.err|resp_i.rty)
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req_o <= 'd0;
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// On an ack, pulse the ack response
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if ((resp_i.ack|resp_i.err|resp_i.rty) & ~aer_i)
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resp_o <= resp_i;
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else
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resp_o <= 'd0;
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end
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endmodule
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