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robfinch |
`timescale 1ns / 1ps
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// ============================================================================
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// Bitmap Controller2
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// - Displays a bitmap from memory.
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//
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//
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// __
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// \\__/ o\ (C) 2008-2015 Robert Finch, Stratford
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@finitron.ca
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// ||
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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// The default base screen address is:
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// $0400000 - the second 4MiB of RAM
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//
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//
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// Verilog 1995
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//
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// ref: XC7a100t-1CSG324
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// 600 LUTs / 3 BRAMs / 425 FF's
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// 196 MHz
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// ============================================================================
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module rtfBitmapController2(
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rst_i,
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s_clk_i, s_cyc_i, s_stb_i, s_ack_o, s_we_i, s_adr_i, s_dat_i, s_dat_o, irq_o,
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m_clk_i, m_cyc_o, m_stb_o, m_ack_i, m_adr_o, m_dat_i,
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vclk, hSync, vSync, blank, rgbPriority, rgbo, xonoff
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);
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parameter pIOAddress = 32'hFFDC5000;
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parameter BM_BASE_ADDR1 = 32'h0040_0000;
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parameter BM_BASE_ADDR2 = 32'h0080_0000;
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parameter REG_CTRL = 10'd0;
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parameter REG_CTRL2 = 10'd1;
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parameter REG_HDISPLAYED = 10'd2;
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parameter REG_VDISPLAYED = 10'd3;
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parameter REG_PAGE1ADDR = 10'd5;
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parameter REG_PAGE2ADDR = 10'd6;
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parameter REG_REFDELAY = 10'd7;
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parameter BPP6 = 3'd0;
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parameter BPP8 = 3'd1;
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parameter BPP12 = 3'd2;
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parameter BPP16 = 3'd3;
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parameter BPP24 = 3'd4;
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parameter BPP30 = 3'd6;
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// SYSCON
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input rst_i; // system reset
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// Peripheral slave port
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input s_clk_i;
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input s_cyc_i;
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input s_stb_i;
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output s_ack_o;
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input s_we_i;
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input [31:0] s_adr_i;
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input [31:0] s_dat_i;
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output [31:0] s_dat_o;
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reg [31:0] s_dat_o;
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output irq_o;
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// Video Master Port
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// Used to read memory via burst access
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input m_clk_i; // system bus interface clock
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output m_cyc_o; // video burst request
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output m_stb_o;
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input m_ack_i; // vid_acknowledge from memory
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output [31:0] m_adr_o; // address for memory access
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input [127:0] m_dat_i; // memory data input
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// Video
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input vclk; // Video clock 85.71 MHz
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input hSync; // start/end of scan line
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input vSync; // start/end of frame
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input blank; // blank the output
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output [1:0] rgbPriority;
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reg [1:0] rgbPriority;
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output [23:0] rgbo; // 24-bit RGB output
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reg [23:0] rgbo;
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input xonoff;
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// IO registers
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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reg m_cyc_o;
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reg m_stb_o;
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reg [31:0] m_adr_o;
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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wire cs = s_cyc_i && s_stb_i && (s_adr_i[31:12]==pIOAddress[31:12]);
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reg ack,ack1;
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always @(posedge s_clk_i)
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begin
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ack1 <= cs;
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ack <= ack1 & cs;
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end
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assign s_ack_o = cs ? (s_we_i ? 1'b1 : ack) : 1'b0;
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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reg [11:0] hDisplayed,vDisplayed;
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reg [31:0] bm_base_addr1,bm_base_addr2;
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reg [2:0] color_depth;
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wire [8:0] fifo_cnt;
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reg onoff;
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reg [1:0] hres,vres;
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reg greyscale;
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reg page;
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reg pals; // palette select
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reg [11:0] hrefdelay;
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reg [11:0] vrefdelay;
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reg [11:0] hctr; // horizontal reference counter
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wire [11:0] hctr1 = hctr - hrefdelay;
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reg [11:0] vctr; // vertical reference counter
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wire [11:0] vctr1 = vctr - vrefdelay;
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reg [31:0] baseAddr; // base address register
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wire [31:0] rgbo1;
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reg [11:0] pixelRow;
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reg [11:0] pixelCol;
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wire [31:0] pal_wo;
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wire [31:0] pal_o;
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always @(page or bm_base_addr1 or bm_base_addr2)
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baseAddr = page ? bm_base_addr2 : bm_base_addr1;
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// Color palette RAM for 8bpp modes
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syncRam512x32_1rw1r upal1
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(
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.wrst(1'b0),
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.wclk(s_clk_i),
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.wce(cs & s_adr_i[11]),
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.we(s_we_i),
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.wadr(s_adr_i[10:2]),
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.i(s_dat_i),
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.wo(pal_wo),
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.rrst(1'b0),
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.rclk(vclk),
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.rce(1'b1),
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.radr({pals,rgbo4[7:0]}),
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.o(pal_o)
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);
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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always @(posedge s_clk_i)
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if (rst_i) begin
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page <= 1'b0;
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pals <= 1'b0;
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hres <= 2'b01;
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vres <= 2'b01;
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hDisplayed <= 12'd672; // must be a multiple of 16
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vDisplayed <= 12'd384;
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onoff <= 1'b1;
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color_depth <= BPP12;
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greyscale <= 1'b0;
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bm_base_addr1 <= BM_BASE_ADDR1;
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bm_base_addr2 <= BM_BASE_ADDR2;
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hrefdelay <= 12'd218;
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vrefdelay <= 12'd27;
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end
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else begin
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if (cs) begin
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if (s_we_i) begin
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casex(s_adr_i[11:2])
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REG_CTRL:
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begin
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onoff <= s_dat_i[0];
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color_depth <= s_dat_i[10:8];
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greyscale <= s_dat_i[11];
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hres <= s_dat_i[17:16];
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vres <= s_dat_i[19:18];
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end
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REG_CTRL2:
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begin
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page <= s_dat_i[16];
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pals <= s_dat_i[17];
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end
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REG_HDISPLAYED: hDisplayed <= s_dat_i[11:0];
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REG_VDISPLAYED: vDisplayed <= s_dat_i[11:0];
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REG_PAGE1ADDR: bm_base_addr1 <= s_dat_i;
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REG_PAGE2ADDR: bm_base_addr2 <= s_dat_i;
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REG_REFDELAY:
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begin
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hrefdelay <= s_dat_i[11:0];
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vrefdelay <= s_dat_i[27:16];
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end
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endcase
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end
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casex(s_adr_i[11:2])
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REG_CTRL:
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begin
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s_dat_o[0] <= onoff;
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s_dat_o[10:8] <= color_depth;
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s_dat_o[11] <= greyscale;
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s_dat_o[17:16] <= hres;
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s_dat_o[19:18] <= vres;
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end
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REG_CTRL2:
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begin
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s_dat_o[16] <= page;
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s_dat_o[17] <= pals;
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end
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REG_HDISPLAYED: s_dat_o <= hDisplayed;
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REG_VDISPLAYED: s_dat_o <= vDisplayed;
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REG_PAGE1ADDR: s_dat_o <= bm_base_addr1;
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REG_PAGE2ADDR: s_dat_o <= bm_base_addr2;
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REG_REFDELAY: s_dat_o <= {vrefdelay,4'h0,hrefdelay};
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10'b1xxx_xxxx_xx: s_dat_o <= pal_wo;
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endcase
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end
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else
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s_dat_o <= 32'd0;
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end
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assign irq_o = 1'b0;
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// Horizontal and Vertical timing reference counters
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// - The memory fetch address is determined from these counters.
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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wire hSyncEdge, vSyncEdge;
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edge_det ed0(.rst(rst_i), .clk(vclk), .ce(1'b1), .i(hSync), .pe(hSyncEdge), .ne(), .ee() );
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edge_det ed1(.rst(rst_i), .clk(vclk), .ce(1'b1), .i(vSync), .pe(vSyncEdge), .ne(), .ee() );
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always @(posedge vclk)
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if (rst_i) hctr <= 1;
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else if (hSyncEdge) hctr <= 1;
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else hctr <= hctr + 1;
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always @(posedge vclk)
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if (rst_i) vctr <= 1;
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else if (vSyncEdge) vctr <= 1;
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else if (hSyncEdge) vctr <= vctr + 1;
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// Pixel row and column are derived from the horizontal and vertical counts.
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always @(posedge vclk)
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case(vres)
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2'b00: pixelRow <= vctr1[11:0];
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2'b01: pixelRow <= vctr1[11:1];
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2'b10: pixelRow <= vctr1[11:2];
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default: pixelRow <= vctr1[11:2];
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endcase
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always @(hctr1)
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case(hres)
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2'b00: pixelCol = hctr1[11:0];
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2'b01: pixelCol = hctr1[11:1];
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2'b10: pixelCol = hctr1[11:2];
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default: pixelCol = hctr1[11:2];
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endcase
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wire vFetch = pixelRow < vDisplayed;
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wire fifo_rst = hctr[11:4]==8'h00;
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wire[23:0] rowOffset = pixelRow * hDisplayed;
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reg [11:0] fetchCol;
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// The following bypasses loading the fifo when all the pixels from a scanline
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// are buffered in the fifo and the pixel row doesn't change. Since the fifo
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// pointers are reset at the beginning of a scanline, the fifo can be used like
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// a cache.
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wire blankEdge;
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edge_det ed2(.rst(rst_i), .clk(m_clk_i), .ce(1'b1), .i(blank), .pe(blankEdge), .ne(), .ee() );
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reg do_loads;
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reg [11:0] opixelRow;
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reg load_fifo;
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always @(posedge m_clk_i)
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load_fifo <= fifo_cnt < 9'd500 && vFetch && onoff && xonoff && fetchCol < hDisplayed && !m_cyc_o && do_loads;
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reg [11:0] hCmp;
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always @(color_depth)
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case(color_depth)
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BPP6: hCmp = 12'd2048;
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BPP8: hCmp = 12'd2048;
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BPP12: hCmp = 12'd1024;
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BPP16: hCmp = 12'd1024;
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BPP24: hCmp = 12'd512;
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default: hCmp = 12'd512;
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endcase
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always @(posedge m_clk_i)
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if (!(hDisplayed < hCmp))
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do_loads <= 1'b1;
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else if (pixelRow != opixelRow)
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do_loads <= 1'b1;
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else if (blankEdge)
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do_loads <= 1'b0;
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reg [31:0] adr;
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always @(posedge m_clk_i)
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if (rst_i) begin
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wb_nack();
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fetchCol <= 12'd0;
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opixelRow <= 12'hFFF;
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end
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else begin
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if (fifo_rst) begin
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315 |
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fetchCol <= 12'd0;
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adr <= baseAddr + rowOffset;
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opixelRow <= pixelRow;
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end
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319 |
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else if (load_fifo) begin
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m_cyc_o <= 1'b1;
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m_stb_o <= 1'b1;
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m_adr_o <= adr;
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end
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324 |
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if (m_cyc_o & m_ack_i) begin
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325 |
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case(color_depth)
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326 |
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BPP6,BPP8: fetchCol <= fetchCol + 12'd16;
|
327 |
|
|
BPP12,BPP16: fetchCol <= fetchCol + 12'd8;
|
328 |
|
|
default: fetchCol <= fetchCol + 12'd4;
|
329 |
|
|
endcase
|
330 |
|
|
wb_nack();
|
331 |
|
|
adr <= adr + 32'd16;
|
332 |
|
|
end
|
333 |
|
|
end
|
334 |
|
|
|
335 |
|
|
task wb_nack;
|
336 |
|
|
begin
|
337 |
|
|
m_cyc_o <= 1'b0;
|
338 |
|
|
m_stb_o <= 1'b0;
|
339 |
|
|
m_adr_o <= 32'h0000_0000;
|
340 |
|
|
end
|
341 |
|
|
endtask
|
342 |
|
|
|
343 |
|
|
reg [11:0] pixelColD1;
|
344 |
|
|
reg [31:0] rgbo2,rgbo3,rgbo4;
|
345 |
|
|
always @(posedge vclk)
|
346 |
|
|
case(color_depth)
|
347 |
|
|
BPP6: rgbo4 <= greyscale ? {3{rgbo2[5:0],2'b00}} : {rgbo2[7:6],6'b00,rgbo2[5:4],6'b00,rgbo2[3:2],6'b00,rgbo2[1:0],6'b00};
|
348 |
|
|
BPP8: rgbo4 <= greyscale ? {3{rgbo2[7:0]}} : rgbo2;
|
349 |
|
|
BPP12: rgbo4 <= {rgbo3[15:14],6'd0,rgbo3[11:8],4'h0,rgbo3[7:4],4'h0,rgbo3[3:0],4'h0};
|
350 |
|
|
BPP16: rgbo4 <= {rgbo3[14:10],3'b0,rgbo3[9:5],3'b0,rgbo3[4:0],3'b0};
|
351 |
|
|
default: rgbo4 <= rgbo1;
|
352 |
|
|
endcase
|
353 |
|
|
|
354 |
|
|
reg rd_fifo,rd_fifo1,rd_fifo2;
|
355 |
|
|
reg de;
|
356 |
|
|
always @(posedge vclk)
|
357 |
|
|
if (rd_fifo1)
|
358 |
|
|
de <= ~blank;
|
359 |
|
|
|
360 |
|
|
always @(posedge vclk)
|
361 |
|
|
if (onoff & xonoff & de) begin
|
362 |
|
|
if (color_depth[2:1]==2'b00 && !greyscale) begin
|
363 |
|
|
rgbo <= pal_o;
|
364 |
|
|
rgbPriority <= pal_o[31:30];
|
365 |
|
|
end
|
366 |
|
|
else begin
|
367 |
|
|
rgbo <= rgbo4[23:0];
|
368 |
|
|
rgbPriority <= rgbo4[31:30];
|
369 |
|
|
end
|
370 |
|
|
end
|
371 |
|
|
else
|
372 |
|
|
rgbo <= 24'd0;
|
373 |
|
|
|
374 |
|
|
// Before the hrefdelay expires, pixelCol will be negative, which is greater
|
375 |
|
|
// than hDisplayed as the value is unsigned. That means that fifo reading is
|
376 |
|
|
// active only during the display area 0 to hDisplayed.
|
377 |
|
|
wire vrd;
|
378 |
|
|
always @(posedge vclk) pixelColD1 <= pixelCol;
|
379 |
|
|
always @(posedge vclk)
|
380 |
|
|
if (pixelCol < hDisplayed + 12'd8)
|
381 |
|
|
case({color_depth[2:1],hres})
|
382 |
|
|
4'b0000: rd_fifo1 <= hctr[1:0]==2'b00; // 4 clocks
|
383 |
|
|
4'b0001: rd_fifo1 <= hctr[2:0]==3'b000; // 8 clocks
|
384 |
|
|
4'b0010: rd_fifo1 <= hctr[3:0]==4'b0000; // 16 clocks
|
385 |
|
|
4'b0011: rd_fifo1 <= hctr[3:0]==4'b0000; // unsupported
|
386 |
|
|
4'b0100: rd_fifo1 <= hctr[0]==1'b0; // 2 clocks
|
387 |
|
|
4'b0101: rd_fifo1 <= hctr[1:0]==2'b00; // 4 clocks
|
388 |
|
|
4'b0110: rd_fifo1 <= hctr[2:0]==3'b000; // 8 clocks (twice as often as a byte)
|
389 |
|
|
4'b0111: rd_fifo1 <= hctr[2:0]==3'b000;
|
390 |
|
|
4'b1000: rd_fifo1 <= 1'b0;
|
391 |
|
|
4'b1001: rd_fifo1 <= 1'b0;
|
392 |
|
|
4'b1010: rd_fifo1 <= 1'b0;
|
393 |
|
|
4'b1011: rd_fifo1 <= 1'b0;
|
394 |
|
|
4'b1100: rd_fifo1 <= 1'b1;
|
395 |
|
|
4'b1101: rd_fifo1 <= hctr[0]==1'b0;
|
396 |
|
|
4'b1110: rd_fifo1 <= hctr[1:0]==2'b00;
|
397 |
|
|
4'b1111: rd_fifo1 <= hctr[1:0]==2'b00;
|
398 |
|
|
endcase
|
399 |
|
|
else
|
400 |
|
|
rd_fifo1 <= 1'b0;
|
401 |
|
|
reg shift,shift1,shift2;
|
402 |
|
|
always @(posedge vclk)
|
403 |
|
|
if (pixelCol < hDisplayed + 12'd8)
|
404 |
|
|
case({color_depth[2:1],hres})
|
405 |
|
|
// shift four times as often as a load
|
406 |
|
|
4'b0000: shift1 <= 1'b1;
|
407 |
|
|
4'b0001: shift1 <= hctr[0]==1'b0;
|
408 |
|
|
4'b0010: shift1 <= hctr[1:0]==2'b00;
|
409 |
|
|
4'b0011: shift1 <= hctr[1:0]==2'b00;
|
410 |
|
|
// shift twice as often as a load
|
411 |
|
|
4'b0100: shift1 <= 1'b1;
|
412 |
|
|
4'b0101: shift1 <= hctr[0]==1'b0;
|
413 |
|
|
4'b0110: shift1 <= hctr[1:0]==2'b00;
|
414 |
|
|
4'b0111: shift1 <= hctr[1:0]==2'b00;
|
415 |
|
|
// unsupported color depth
|
416 |
|
|
4'b1000: shift1 <= 1'b0;
|
417 |
|
|
4'b1001: shift1 <= 1'b0;
|
418 |
|
|
4'b1010: shift1 <= 1'b0;
|
419 |
|
|
4'b1011: shift1 <= 1'b0;
|
420 |
|
|
// nothing to shift (all loads)
|
421 |
|
|
4'b1100: shift1 <= 1'b0;
|
422 |
|
|
4'b1101: shift1 <= 1'b0;
|
423 |
|
|
4'b1110: shift1 <= 1'b0;
|
424 |
|
|
4'b1111: shift1 <= 1'b0;
|
425 |
|
|
endcase
|
426 |
|
|
always @(posedge vclk) shift2 <= shift1;
|
427 |
|
|
always @(posedge vclk) shift <= shift2;
|
428 |
|
|
always @(posedge vclk) rd_fifo2 <= rd_fifo1;
|
429 |
|
|
always @(posedge vclk) rd_fifo <= rd_fifo2;
|
430 |
|
|
always @(posedge vclk)
|
431 |
|
|
if (rd_fifo)
|
432 |
|
|
rgbo2 <= rgbo1;
|
433 |
|
|
else if (shift)
|
434 |
|
|
rgbo2 <= {8'h00,rgbo2[31:8]};
|
435 |
|
|
always @(posedge vclk)
|
436 |
|
|
if (rd_fifo)
|
437 |
|
|
rgbo3 <= rgbo1;
|
438 |
|
|
else if (shift)
|
439 |
|
|
rgbo3 <= {16'h0000,rgbo3[31:16]};
|
440 |
|
|
|
441 |
|
|
rtfVideoFifo2 uf1
|
442 |
|
|
(
|
443 |
|
|
.rst(fifo_rst),
|
444 |
|
|
.wclk(m_clk_i),
|
445 |
|
|
.wr(m_cyc_o & m_ack_i),
|
446 |
|
|
.di(m_dat_i),
|
447 |
|
|
.rclk(vclk),
|
448 |
|
|
.rd(rd_fifo),
|
449 |
|
|
.do(rgbo1),
|
450 |
|
|
.cnt(fifo_cnt)
|
451 |
|
|
);
|
452 |
|
|
|
453 |
|
|
endmodule
|
454 |
|
|
|