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[/] [rtfsimpleuart/] [trunk/] [doc/] [rtfSimpleUartUsage.txt] - Blame information for rev 11

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1 9 robfinch
 
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        To use:
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        Set the pClkFreq parameter to the frequency of the system
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        clock (clk_i). This can be done when the core is instanced.
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    1) set the baud rate value in the clock multiplier
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    registers (CM1,2,3). A default multiplier value may
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    be specified using the pClkMul parameter, so it
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    doesn't have to be programmed at run time. (Note the
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    pBaud parameter may also be set, but it doesn't work
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    in all cases due to arithmetic limitations).
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    2) enable communication by activating the rts, and
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    dtr signals in the modem control register. These
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    signals are defaulted to be active on reset, so they
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    may not need to be set. The pRts and pDtr parameters
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    may be used to change the default setting.
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    3) use interrupts or poll the status register to
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    determine when to transmit or receive a byte of data
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    4) read / write the transmit / recieve data buffer
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    for communication.
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    Notes:
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        This core only supports a single transmission /
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    reception format: 1 start, 8 data, and 1 stop bit (no
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    parity).
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        The baud rate generator uses a 24 bit harmonic
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    frequency synthesizer. Compute the multiplier value
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    as if a 32 bit value was needed, then take the upper
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    24 bits of the value. (The number of significant bits
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    in the value determine the minimum frequency
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    resolution or the precision of the value).
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                                baud rate * 16
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        value = -----------------------
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                        (clock frequency / 2^32)
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                eg                      38400 * 16
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                value = -----------------------
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                                (28.63636MHz / 2^32)
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                                = 92149557.65
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                                = 057E1736 (hex)
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                taking the upper 24 bits
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                                top 24 = 057E17
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                                                = 359959
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                so the value needed to be programmed into the register
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        for 38.4k baud is 57E17 (hex)
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                eg      CM0 = 0 (not used)
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                        CM1 = 17 hex
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                        CM2 = 7E hex
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                        CM3 = 05 hex
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        Register Description
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        reg
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                TRB - transmit / receive buffer
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                transmit / receive buffer
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                write   - write to transmit buffer
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                read    - read from receive buffer
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        1       read only (RO)
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                LS      - line status register
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                bit 0 = receiver not empty, this bit is set if there is
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                                any data available in the receiver fifo
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                bit 1 = overrun, this bit is set if receiver overrun occurs
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                bit 3 = framing error, this bit is set if there was a
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                                framing error with the current byte in the receiver
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                                buffer.
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                bit 5 = transmitter not full, this bit is set if the transmitter
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                                can accept more data
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                bit 6 = transmitter empty, this bit is set if the transmitter is
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                                completely empty
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        2       MS      - modem status register (RO)
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                writing to the modem status register clears the change
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                indicators, which should clear a modem status interrupt
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                bit 3 = change on dcd signal
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                bit 4 = cts signal level
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                bit 5 = dsr signal level
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                bit 6 = ri signal level
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                bit 7 = dcd signal level
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        3       IS      - interrupt status register (RO)
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                bit 0-4 = mailbox number
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                bit 0,1 = 00
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                bit 2-4 = encoded interrupt value
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                bit 5-6 = not used, reserved
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                bit 7 = 1 = interrupt pending, 0 = no interrupt
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        4       IE      - interrupt enable register (RW)
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                bit 0 = receive interrupt (data present)
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                bit 1 = transmit interrupt (data empty)
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                bit 3 = modem status (dcd) register change
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                bit 5-7 = unused, reserved
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        5       FF      - frame format register         (RW)
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                this register doesn't do anything in the simpleUart
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                but is reserved for compatiblity with the more
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                advanced uart
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        6       MC      - modem control register (RW)
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                bit 0 = dtr signal level output
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                bit 1 = rts signal level output
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        7       - control register
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                bit 0 = hardware flow control,
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                        when this bit is set, the transmitter output is
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                        controlled by the cts signal line automatically
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                * Clock multiplier steps the 16xbaud clock frequency
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                in increments of 1/2^32 of the clk_i input using a
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                harmonic frequency synthesizer
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                eg. to get a 9600 baud 16x clock (153.6 kHz) with a
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                27.175 MHz clock input,
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                value  = upper24(9600 * 16  / (27.175MHz / 2^32))
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                Higher frequency baud rates will exhibit more jitter
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                on the 16x clock, but this will mostly be masked by the
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                16x clock factor.
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        8       CM0     - Clock Multiplier byte 0 (RW)
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                this is the least significant byte
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                of the clock multiplier value
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                this register is not used unless the clock
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                multiplier is set to contain 32 bit values
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        9       CM1 - Clock Multiplier byte 1   (RW)
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                this is the third most significant byte
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                of the clock multiplier value
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                this register is not used unless the clock
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                multiplier is set to contain 24 or 32 bit values
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        10      CM2 - Clock Multiplier byte 2   (RW)
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                this is the second most significant byte of the clock
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                multiplier value
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        11      CM3     - Clock Multiplier byte 3       (RW)
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                this is the most significant byte of the multiplier value
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        12      FC      - Fifo control register         (RW)
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                this register doesnt' do anything in the simpleUart
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                but is reserved for compatibility with the more
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                advanced uart
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        13-14   reserved registers
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        15      SPR     - scratch pad register (RW)
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SAMPLE SOFTWARE USAGE:
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        This is an extract of code from Tiny Basic 68000. The UART is in use as the auxilliary
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port for tiny basic. The sample is in 68000 assembly language. The sample uses default
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settings of the UART, which is 19.2k baud, so there is no initialization required.
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;==============================================================================
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;==============================================================================
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UART            EQU             0xFFDC0A00
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UART_LS         EQU             UART+1
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UART_CTRL       EQU             UART+7
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;*
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;* ===== Output character to the host (Port 2) from register D0
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;*      (Preserves all registers.)
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;*
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AUXOUT:
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        BTST    #5,UART_LS      ;is port ready for a character?
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        BEQ             AUXOUT          ;if not, wait for it
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        MOVE.B  D0,UART         ;out it goes.
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        RTS
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;*
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;* ===== Input a character from the host into register D0 (or
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;*      return Zero status if there's no character available).
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;*
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AUXIN:
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        BTST    #0,UART_LS      ;is character ready?
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        BEQ             AXIRET          ;if not, return Zero status
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        MOVE.B  UART,D0         ;else get the character
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        AND.B   #0x7F,D0        ;zero out the high bit
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AXIRET:
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        RTS
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;==============================================================================
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;==============================================================================
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EXAMPLE OF CORE INSTANCING:
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The core needs to know the clock rate.
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rtfSimpleUart #(16666667) uuart
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(
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        // WISHBONE Slave interface
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        .rst_i(rst),                    // reset
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        .clk_i(clk25),                  // eg 100.7MHz
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        .cyc_i(sys_cyc),                // cycle valid
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        .stb_i(sys_stb),                // strobe
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        .we_i(sys_we),                  // 1 = write
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        .adr_i(cpu_adr),        // register address
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        .dat_i(dbo[7:0]),               // data input bus
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        .dat_o(uart_dbo),               // data output bus
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        .ack_o(uart_ack),               // transfer acknowledge
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        .vol_o(),                               // volatile register selected
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        .irq_o(),                               // interrupt request
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        //----------------
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        .cts_ni(1'b0),          // clear to send - active low - (flow control)
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        .rts_no(),                      // request to send - active low - (flow control)
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        .dsr_ni(1'b0),          // data set ready - active low
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        .dcd_ni(1'b0),          // data carrier detect - active low
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        .dtr_no(),                      // data terminal ready - active low
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        .rxd_i(rxd),                    // serial data in
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        .txd_o(txd),                    // serial data out
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        .data_present_o()
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);
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