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[/] [rtfsimpleuart/] [trunk/] [doc/] [rtfSimpleUartWishboneDatasheet.txt] - Blame information for rev 15
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|WISHBONE Datasheet
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|WISHBONE SoC Architecture Specification, Revision B.3
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|Description: Specifications:
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|General Description: simple UART core
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|Supported Cycles: SLAVE,READ/WRITE
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| SLAVE,BLOCK READ/WRITE
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| SLAVE,RMW
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|Data port, size: 8 bit
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|Data port, granularity: 8 bit
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|Data port, maximum operand size: 8 bit
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|Data transfer ordering: Undefined
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|Data transfer sequencing: Undefined
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|Clock frequency constraints: none
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|Supported signal list and Signal Name WISHBONE equiv.
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|cross reference to equivalent ack_o ACK_O
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|WISHBONE signals adr_i[3:0] ADR_I()
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| clk_i CLK_I
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| rst_i RST_I()
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| dat_i(7:0) DAT_I()
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| dat_o(7:0) DAT_O()
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| cyc_i CYC_I
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| stb_i STB_I
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| we_i WE_I
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|Special requirements:
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