OpenCores
URL https://opencores.org/ocsvn/rtfsimpleuart/rtfsimpleuart/trunk

Subversion Repositories rtfsimpleuart

[/] [rtfsimpleuart/] [trunk/] [rtl/] [verilog/] [edge_det.v] - Blame information for rev 7

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 7 robfinch
/* ============================================================================
2
        2007  Robert Finch
3
        rob@birdcomputer.ca
4
 
5
        edge_det.v
6
 
7
    This source code is available for evaluation and validation purposes
8
    only. This copyright statement and disclaimer must remain present in
9
    the file.
10
 
11
 
12
        NO WARRANTY.
13
    THIS Work, IS PROVIDEDED "AS IS" WITH NO WARRANTIES OF ANY KIND, WHETHER
14
    EXPRESS OR IMPLIED. The user must assume the entire risk of using the
15
    Work.
16
 
17
    IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
18
    INCIDENTAL, CONSEQUENTIAL, OR PUNITIVE DAMAGES WHATSOEVER RELATING TO
19
    THE USE OF THIS WORK, OR YOUR RELATIONSHIP WITH THE AUTHOR.
20
 
21
    IN ADDITION, IN NO EVENT DOES THE AUTHOR AUTHORIZE YOU TO USE THE WORK
22
    IN APPLICATIONS OR SYSTEMS WHERE THE WORK'S FAILURE TO PERFORM CAN
23
    REASONABLY BE EXPECTED TO RESULT IN A SIGNIFICANT PHYSICAL INJURY, OR IN
24
    LOSS OF LIFE. ANY SUCH USE BY YOU IS ENTIRELY AT YOUR OWN RISK, AND YOU
25
    AGREE TO HOLD THE AUTHOR AND CONTRIBUTORS HARMLESS FROM ANY CLAIMS OR
26
    LOSSES RELATING TO SUCH UNAUTHORIZED USE.
27
 
28
 
29
    Notes:
30
 
31
        Edge detector
32
        This little core detects an edge (positive, negative, and
33
        either) in the input signal.
34
 
35
        Verilog 1995
36
        Webpack 9.2 xc3S1000-4ft256
37
        3 LUTs / 2 slices / 9.1ns
38
============================================================================ */
39
 
40
module edge_det(rst, clk, ce, i, pe, ne, ee);
41
input rst;              // reset
42
input clk;              // clock
43
input ce;               // clock enable
44
input i;                // input signal
45
output pe;              // positive transition detected
46
output ne;              // negative transition detected
47
output ee;              // either edge (positive or negative) transition detected
48
 
49
reg ed;
50
always @(posedge clk)
51
        if (rst)
52
                ed <= 1'b0;
53
        else if (ce)
54
                ed <= i;
55
 
56
assign pe = ~ed & i;    // positive: was low and is now high
57
assign ne = ed & ~i;    // negative: was high and is now low
58
assign ee = ed ^ i;             // either: signal is now opposite to what it was
59
 
60
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.