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robfinch |
/* ============================================================================
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2011 Robert Finch
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robfinch@<remove>sympatico.ca
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rtfSimpleUartRx.v
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This source code is available for evaluation and validation purposes
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only. This copyright statement and disclaimer must remain present in
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the file.
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NO WARRANTY.
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THIS Work, IS PROVIDEDED "AS IS" WITH NO WARRANTIES OF ANY KIND, WHETHER
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EXPRESS OR IMPLIED. The user must assume the entire risk of using the
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Work.
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IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
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INCIDENTAL, CONSEQUENTIAL, OR PUNITIVE DAMAGES WHATSOEVER RELATING TO
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THE USE OF THIS WORK, OR YOUR RELATIONSHIP WITH THE AUTHOR.
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IN ADDITION, IN NO EVENT DOES THE AUTHOR AUTHORIZE YOU TO USE THE WORK
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IN APPLICATIONS OR SYSTEMS WHERE THE WORK'S FAILURE TO PERFORM CAN
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REASONABLY BE EXPECTED TO RESULT IN A SIGNIFICANT PHYSICAL INJURY, OR IN
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LOSS OF LIFE. ANY SUCH USE BY YOU IS ENTIRELY AT YOUR OWN RISK, AND YOU
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AGREE TO HOLD THE AUTHOR AND CONTRIBUTORS HARMLESS FROM ANY CLAIMS OR
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LOSSES RELATING TO SUCH UNAUTHORIZED USE.
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Simple UART receiver core
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Features:
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false start bit detection
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framing error detection
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overrun state detection
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resynchronization on every character
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fixed format 1 start - 8 data - 1 stop bits
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uses 16x clock rate
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This core may be used as a standalone peripheral
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on a SoC bus if all that is desired is recieve
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capability. It requires a 16x baud rate clock.
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+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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|WISHBONE Datasheet
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|WISHBONE SoC Architecture Specification, Revision B.3
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|Description: Specifications:
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+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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|General Description: simple serial UART receiver
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+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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|Supported Cycles: SLAVE,READ
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| SLAVE,BLOCK READ
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+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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|Data port, size: 8 bit
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|Data port, granularity: 8 bit
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|Data port, maximum operand size: 8 bit
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|Data transfer ordering: Undefined
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|Data transfer sequencing: Undefined
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+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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|Clock frequency constraints: none
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+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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|Supported signal list and Signal Name WISHBONE equiv.
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|cross reference to equivalent ack_o ACK_O
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|WISHBONE signals
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| clk_i CLK_I
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| rst_i RST_I
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| dat_o(7:0) DAT_O()
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| cyc_i CYC_I
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| stb_i STB_I
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| we_i WE_I
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+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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|Special requirements:
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+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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Ref: Spartan3 -4
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27 LUTs / 24 slices / 170 MHz
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============================================================================ */
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`define IDLE 0
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`define CNT 1
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module rtfSimpleUartRx(
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// WISHBONE SoC bus interface
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input rst_i, // reset
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input clk_i, // clock
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input cyc_i, // cycle is valid
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input stb_i, // strobe
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output ack_o, // data is ready
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input we_i, // write (this signal is used to qualify reads)
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output [7:0] dat_o, // data out
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//------------------------
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input cs_i, // chip select
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input baud16x_ce, // baud rate clock enable
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input clear, // clear reciever
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input rxd, // external serial input
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output reg data_present, // data present in fifo
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output reg frame_err, // framing error
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output reg overrun // receiver overrun
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);
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// variables
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reg [3:0] rxdd; // synchronizer flops
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reg [7:0] cnt; // sample bit rate counter
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reg [9:0] rx_data; // working receive data register
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reg state; // state machine
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reg wf; // buffer write
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reg [7:0] dat;
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assign ack_o = cyc_i & stb_i & cs_i;
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assign dat_o = ack_o ? dat : 8'b0;
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// update data register
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always @(posedge clk_i)
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if (wf) dat <= rx_data[8:1];
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// on a read clear the data present status
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// but set the status when the data register
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// is updated by the receiver
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always @(posedge clk_i)
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if (wf) data_present <= 1;
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else if (ack_o & ~we_i) data_present <= 0;
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// Three stage synchronizer to synchronize incoming data to
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// the local clock (avoids metastability).
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always @(posedge clk_i)
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rxdd <= {rxdd[2:0],rxd};
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always @(posedge clk_i) begin
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if (rst_i) begin
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state <= `IDLE;
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wf <= 1'b0;
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overrun <= 1'b0;
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end
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else begin
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// Clear write flag
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wf <= 1'b0;
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if (clear) begin
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wf <= 1'b0;
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state <= `IDLE;
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overrun <= 1'b0;
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end
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else if (baud16x_ce) begin
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case (state)
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// Sit in the idle state until a start bit is
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// detected.
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`IDLE:
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// look for start bit
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if (~rxdd[3])
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state <= `CNT;
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`CNT:
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begin
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// End of the frame ?
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// - check for framing error
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// - write data to read buffer
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if (cnt==8'h97)
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begin
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frame_err <= ~rxdd[3];
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if (!data_present)
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wf <= 1'b1;
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else
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overrun <= 1'b1;
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end
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// Switch back to the idle state a little
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// bit too soon.
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if (cnt==8'h9D)
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state <= `IDLE;
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// On start bit check make sure the start
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// bit is low, otherwise go back to the
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// idle state because it's a false start.
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if (cnt==8'h07 && rxdd[3])
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state <= `IDLE;
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if (cnt[3:0]==4'h7)
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rx_data <= {rxdd[3],rx_data[9:1]};
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end
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endcase
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end
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end
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end
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// bit rate counter
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always @(posedge clk_i)
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if (baud16x_ce) begin
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if (state == `IDLE)
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cnt <= 0;
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else
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cnt <= cnt + 1;
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end
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endmodule
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