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[/] [rtfsimpleuart/] [trunk/] [rtl/] [verilog/] [rtfSimpleUartTx.v] - Blame information for rev 12

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/* ============================================================================
        2011  Robert Finch
        robfinch@<remove>sympatico.ca
 
        rtfSimpleUartTx.v
 
    This source code is available for evaluation and validation purposes
    only. This copyright statement and disclaimer must remain present in
    the file.
 
 
        NO WARRANTY.
    THIS Work, IS PROVIDEDED "AS IS" WITH NO WARRANTIES OF ANY KIND, WHETHER
    EXPRESS OR IMPLIED. The user must assume the entire risk of using the
    Work.
 
    IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
    INCIDENTAL, CONSEQUENTIAL, OR PUNITIVE DAMAGES WHATSOEVER RELATING TO
    THE USE OF THIS WORK, OR YOUR RELATIONSHIP WITH THE AUTHOR.
 
    IN ADDITION, IN NO EVENT DOES THE AUTHOR AUTHORIZE YOU TO USE THE WORK
    IN APPLICATIONS OR SYSTEMS WHERE THE WORK'S FAILURE TO PERFORM CAN
    REASONABLY BE EXPECTED TO RESULT IN A SIGNIFICANT PHYSICAL INJURY, OR IN
    LOSS OF LIFE. ANY SUCH USE BY YOU IS ENTIRELY AT YOUR OWN RISK, AND YOU
    AGREE TO HOLD THE AUTHOR AND CONTRIBUTORS HARMLESS FROM ANY CLAIMS OR
    LOSSES RELATING TO SUCH UNAUTHORIZED USE.
 
 
                Simple uart transmitter core.
                Features:
                        Fixed format 1 start - 8 data - 1 stop bits
 
 
        +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
        |WISHBONE Datasheet
        |WISHBONE SoC Architecture Specification, Revision B.3
        |
        |Description:                                           Specifications:
        +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
        |General Description:                           simple serial UART transmitter
        +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
        |Supported Cycles:                                      SLAVE,WRITE
        |                                                                       SLAVE,BLOCK WRITE
        +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
        |Data port, size:                                       8 bit
        |Data port, granularity:                        8 bit
        |Data port, maximum operand size:       8 bit
        |Data transfer ordering:                        Undefined
        |Data transfer sequencing:                      Undefined
        +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
        |Clock frequency constraints:           none
    |      Baud Generates by X16 or X8 CLK_I depends on baud8x pin
        +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
        |Supported signal list and                      Signal Name             WISHBONE equiv.
        |cross reference to equivalent          ack_o                   ACK_O
        |WISHBONE signals
        |                                                                       clk_i                   CLK_I
        |                                   rst_i           RST_I
        |                                                                       dat_i[7:0]              DAT_I()
        |                                                                       cyc_i                   CYC_I
        |                                                                       stb_i                   STB_I
        |                                                                       we_i                    WE_I
        |
        +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
        |Special requirements:
        +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
 
 
        REF: Spartan3 - 4
        30 LUTs / 23 slices / 165MHz
============================================================================ */
 
module rtfSimpleUartTx(
        // WISHBONE SoC bus interface
        input rst_i,            // reset
        input clk_i,            // clock
        input cyc_i,            // cycle valid
        input stb_i,            // strobe
        output ack_o,           // transfer done
        input we_i,                     // write transmitter
        input [7:0] dat_i,       // data in
        //--------------------
        input cs_i,                     // chip select
        input baud16x_ce,       // baud rate clock enable
    input tri0 baud8x,       // switches to mode baudX8
        input cts,                      // clear to send
        output txd,                     // external serial output
        output reg empty,       // buffer is empty
    output reg txc          // tx complete flag
);
 
reg [9:0] tx_data;       // transmit data working reg (raw)
reg [7:0] fdo;           // data output
reg [7:0] cnt;           // baud clock counter
reg rd;
 
wire isX8;
buf(isX8, baud8x);
reg  modeX8;
 
assign ack_o = cyc_i & stb_i & cs_i;
assign txd = tx_data[0];
 
always @(posedge clk_i)
        if (ack_o & we_i) fdo <= dat_i;
 
// set full / empty status
always @(posedge clk_i)
        if (rst_i) empty <= 1;
        else begin
        if (ack_o & we_i) empty <= 0;
        else if (rd) empty <= 1;
        end
 
`define CNT_FINISH (8'h9F)
always @(posedge clk_i)
        if (rst_i) begin
                cnt <= `CNT_FINISH;
                rd <= 0;
                tx_data <= 10'h3FF;
        txc <= 1'b1;
        modeX8 <= 1'b0;
        end
        else begin
 
                rd <= 0;
 
                if (baud16x_ce) begin
 
                        // Load next data ?
                        if (cnt==`CNT_FINISH) begin
                modeX8 <= isX8;
                                if (!empty && cts) begin
                                        tx_data <= {1'b1,fdo,1'b0};
                                        rd <= 1;
                    cnt <= modeX8;
                    txc <= 1'b0;
                                end
                else
                    txc <= 1'b1;
                        end
                        // Shift the data out. LSB first.
                        else begin
                cnt[7:1] <= cnt[7:1] + cnt[0];
                cnt[0] <= ~cnt[0] | (modeX8);
 
                if (cnt[3:0]==4'hF)
                    tx_data <= {1'b1,tx_data[9:1]};
            end
                end
        end
 
endmodule

Line No.	Rev	Author	Line
1	4	robfinch	`/* ============================================================================`
2			`2011 Robert Finch`
3			`robfinch@<remove>sympatico.ca`
4
5			`rtfSimpleUartTx.v`
6
7			`This source code is available for evaluation and validation purposes`
8			`only. This copyright statement and disclaimer must remain present in`
9			`the file.`
10
11
12			`NO WARRANTY.`
13			`THIS Work, IS PROVIDEDED "AS IS" WITH NO WARRANTIES OF ANY KIND, WHETHER`
14			`EXPRESS OR IMPLIED. The user must assume the entire risk of using the`
15			`Work.`
16
17			`IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY`
18			`INCIDENTAL, CONSEQUENTIAL, OR PUNITIVE DAMAGES WHATSOEVER RELATING TO`
19			`THE USE OF THIS WORK, OR YOUR RELATIONSHIP WITH THE AUTHOR.`
20
21			`IN ADDITION, IN NO EVENT DOES THE AUTHOR AUTHORIZE YOU TO USE THE WORK`
22			`IN APPLICATIONS OR SYSTEMS WHERE THE WORK'S FAILURE TO PERFORM CAN`
23			`REASONABLY BE EXPECTED TO RESULT IN A SIGNIFICANT PHYSICAL INJURY, OR IN`
24			`LOSS OF LIFE. ANY SUCH USE BY YOU IS ENTIRELY AT YOUR OWN RISK, AND YOU`
25			`AGREE TO HOLD THE AUTHOR AND CONTRIBUTORS HARMLESS FROM ANY CLAIMS OR`
26			`LOSSES RELATING TO SUCH UNAUTHORIZED USE.`
27
28
29			`Simple uart transmitter core.`
30			`Features:`
31			`Fixed format 1 start - 8 data - 1 stop bits`
32
33
34			`+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -`
35			`\|WISHBONE Datasheet`
36			`\|WISHBONE SoC Architecture Specification, Revision B.3`
37			`\|`
38			`\|Description: Specifications:`
39			`+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -`
40			`\|General Description: simple serial UART transmitter`
41			`+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -`
42			`\|Supported Cycles: SLAVE,WRITE`
43			`\| SLAVE,BLOCK WRITE`
44			`+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -`
45			`\|Data port, size: 8 bit`
46			`\|Data port, granularity: 8 bit`
47			`\|Data port, maximum operand size: 8 bit`
48			`\|Data transfer ordering: Undefined`
49			`\|Data transfer sequencing: Undefined`
50			`+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -`
51			`\|Clock frequency constraints: none`
52	12	AlexRayne	`\| Baud Generates by X16 or X8 CLK_I depends on baud8x pin`
53	4	robfinch	`+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -`
54			`\|Supported signal list and Signal Name WISHBONE equiv.`
55			`\|cross reference to equivalent ack_o ACK_O`
56			`\|WISHBONE signals`
57			`\| clk_i CLK_I`
58			`\| rst_i RST_I`
59			`\| dat_i[7:0] DAT_I()`
60			`\| cyc_i CYC_I`
61			`\| stb_i STB_I`
62			`\| we_i WE_I`
63			`\|`
64			`+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -`
65			`\|Special requirements:`
66			`+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -`
67
68
69			`REF: Spartan3 - 4`
70			`30 LUTs / 23 slices / 165MHz`
71			`============================================================================ */`
72
73			`module rtfSimpleUartTx(`
74			`// WISHBONE SoC bus interface`
75			`input rst_i, // reset`
76			`input clk_i, // clock`
77			`input cyc_i, // cycle valid`
78			`input stb_i, // strobe`
79			`output ack_o, // transfer done`
80			`input we_i, // write transmitter`
81			`input [7:0] dat_i, // data in`
82			`//--------------------`
83			`input cs_i, // chip select`
84			`input baud16x_ce, // baud rate clock enable`
85	12	AlexRayne	`input tri0 baud8x, // switches to mode baudX8`
86	4	robfinch	`input cts, // clear to send`
87			`output txd, // external serial output`
88	12	AlexRayne	`output reg empty, // buffer is empty`
89			`output reg txc // tx complete flag`
90	4	robfinch	`);`
91
92			`reg [9:0] tx_data; // transmit data working reg (raw)`
93			`reg [7:0] fdo; // data output`
94			`reg [7:0] cnt; // baud clock counter`
95			`reg rd;`
96
97	12	AlexRayne	`wire isX8;`
98			`buf(isX8, baud8x);`
99			`reg modeX8;`
100
101	4	robfinch	`assign ack_o = cyc_i & stb_i & cs_i;`
102			`assign txd = tx_data[0];`
103
104			`always @(posedge clk_i)`
105			`if (ack_o & we_i) fdo <= dat_i;`
106
107			`// set full / empty status`
108			`always @(posedge clk_i)`
109			`if (rst_i) empty <= 1;`
110			`else begin`
111			`if (ack_o & we_i) empty <= 0;`
112			`else if (rd) empty <= 1;`
113			`end`
114
115	12	AlexRayne	`define CNT_FINISH (8'h9F)
116	4	robfinch	`always @(posedge clk_i)`
117			`if (rst_i) begin`
118	12	AlexRayne	cnt <= `CNT_FINISH;
119	4	robfinch	`rd <= 0;`
120			`tx_data <= 10'h3FF;`
121	12	AlexRayne	`txc <= 1'b1;`
122			`modeX8 <= 1'b0;`
123	4	robfinch	`end`
124			`else begin`
125
126			`rd <= 0;`
127
128			`if (baud16x_ce) begin`
129
130			`// Load next data ?`
131	12	AlexRayne	if (cnt==`CNT_FINISH) begin
132			`modeX8 <= isX8;`
133	4	robfinch	`if (!empty && cts) begin`
134			`tx_data <= {1'b1,fdo,1'b0};`
135			`rd <= 1;`
136	12	AlexRayne	`cnt <= modeX8;`
137			`txc <= 1'b0;`
138	4	robfinch	`end`
139	12	AlexRayne	`else`
140			`txc <= 1'b1;`
141	4	robfinch	`end`
142			`// Shift the data out. LSB first.`
143	12	AlexRayne	`else begin`
144			`cnt[7:1] <= cnt[7:1] + cnt[0];`
145			`cnt[0] <= ~cnt[0] \| (modeX8);`
146	4	robfinch
147	12	AlexRayne	`if (cnt[3:0]==4'hF)`
148			`tx_data <= {1'b1,tx_data[9:1]};`
149			`end`
150	4	robfinch	`end`
151			`end`
152
153			`endmodule`

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[/] [rtfsimpleuart/] [trunk/] [rtl/] [verilog/] [rtfSimpleUartTx.v] - Blame information for rev 12