| 1 |
4 |
robfinch |
/* ============================================================================
|
| 2 |
|
|
2011 Robert Finch
|
| 3 |
|
|
robfinch@<remove>sympatico.ca
|
| 4 |
|
|
|
| 5 |
|
|
rtfSimpleUartTx.v
|
| 6 |
|
|
|
| 7 |
|
|
This source code is available for evaluation and validation purposes
|
| 8 |
|
|
only. This copyright statement and disclaimer must remain present in
|
| 9 |
|
|
the file.
|
| 10 |
|
|
|
| 11 |
|
|
|
| 12 |
|
|
NO WARRANTY.
|
| 13 |
|
|
THIS Work, IS PROVIDEDED "AS IS" WITH NO WARRANTIES OF ANY KIND, WHETHER
|
| 14 |
|
|
EXPRESS OR IMPLIED. The user must assume the entire risk of using the
|
| 15 |
|
|
Work.
|
| 16 |
|
|
|
| 17 |
|
|
IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
|
| 18 |
|
|
INCIDENTAL, CONSEQUENTIAL, OR PUNITIVE DAMAGES WHATSOEVER RELATING TO
|
| 19 |
|
|
THE USE OF THIS WORK, OR YOUR RELATIONSHIP WITH THE AUTHOR.
|
| 20 |
|
|
|
| 21 |
|
|
IN ADDITION, IN NO EVENT DOES THE AUTHOR AUTHORIZE YOU TO USE THE WORK
|
| 22 |
|
|
IN APPLICATIONS OR SYSTEMS WHERE THE WORK'S FAILURE TO PERFORM CAN
|
| 23 |
|
|
REASONABLY BE EXPECTED TO RESULT IN A SIGNIFICANT PHYSICAL INJURY, OR IN
|
| 24 |
|
|
LOSS OF LIFE. ANY SUCH USE BY YOU IS ENTIRELY AT YOUR OWN RISK, AND YOU
|
| 25 |
|
|
AGREE TO HOLD THE AUTHOR AND CONTRIBUTORS HARMLESS FROM ANY CLAIMS OR
|
| 26 |
|
|
LOSSES RELATING TO SUCH UNAUTHORIZED USE.
|
| 27 |
|
|
|
| 28 |
|
|
|
| 29 |
|
|
Simple uart transmitter core.
|
| 30 |
|
|
Features:
|
| 31 |
|
|
Fixed format 1 start - 8 data - 1 stop bits
|
| 32 |
|
|
|
| 33 |
|
|
|
| 34 |
|
|
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
| 35 |
|
|
|WISHBONE Datasheet
|
| 36 |
|
|
|WISHBONE SoC Architecture Specification, Revision B.3
|
| 37 |
|
|
|
|
| 38 |
|
|
|Description: Specifications:
|
| 39 |
|
|
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
| 40 |
|
|
|General Description: simple serial UART transmitter
|
| 41 |
|
|
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
| 42 |
|
|
|Supported Cycles: SLAVE,WRITE
|
| 43 |
|
|
| SLAVE,BLOCK WRITE
|
| 44 |
|
|
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
| 45 |
|
|
|Data port, size: 8 bit
|
| 46 |
|
|
|Data port, granularity: 8 bit
|
| 47 |
|
|
|Data port, maximum operand size: 8 bit
|
| 48 |
|
|
|Data transfer ordering: Undefined
|
| 49 |
|
|
|Data transfer sequencing: Undefined
|
| 50 |
|
|
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
| 51 |
|
|
|Clock frequency constraints: none
|
| 52 |
|
|
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
| 53 |
|
|
|Supported signal list and Signal Name WISHBONE equiv.
|
| 54 |
|
|
|cross reference to equivalent ack_o ACK_O
|
| 55 |
|
|
|WISHBONE signals
|
| 56 |
|
|
| clk_i CLK_I
|
| 57 |
|
|
| rst_i RST_I
|
| 58 |
|
|
| dat_i[7:0] DAT_I()
|
| 59 |
|
|
| cyc_i CYC_I
|
| 60 |
|
|
| stb_i STB_I
|
| 61 |
|
|
| we_i WE_I
|
| 62 |
|
|
|
|
| 63 |
|
|
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
| 64 |
|
|
|Special requirements:
|
| 65 |
|
|
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
| 66 |
|
|
|
| 67 |
|
|
|
| 68 |
|
|
REF: Spartan3 - 4
|
| 69 |
|
|
30 LUTs / 23 slices / 165MHz
|
| 70 |
|
|
============================================================================ */
|
| 71 |
|
|
|
| 72 |
|
|
module rtfSimpleUartTx(
|
| 73 |
|
|
// WISHBONE SoC bus interface
|
| 74 |
|
|
input rst_i, // reset
|
| 75 |
|
|
input clk_i, // clock
|
| 76 |
|
|
input cyc_i, // cycle valid
|
| 77 |
|
|
input stb_i, // strobe
|
| 78 |
|
|
output ack_o, // transfer done
|
| 79 |
|
|
input we_i, // write transmitter
|
| 80 |
|
|
input [7:0] dat_i, // data in
|
| 81 |
|
|
//--------------------
|
| 82 |
|
|
input cs_i, // chip select
|
| 83 |
|
|
input baud16x_ce, // baud rate clock enable
|
| 84 |
|
|
input cts, // clear to send
|
| 85 |
|
|
output txd, // external serial output
|
| 86 |
|
|
output reg empty // buffer is empty
|
| 87 |
|
|
);
|
| 88 |
|
|
|
| 89 |
|
|
reg [9:0] tx_data; // transmit data working reg (raw)
|
| 90 |
|
|
reg [7:0] fdo; // data output
|
| 91 |
|
|
reg [7:0] cnt; // baud clock counter
|
| 92 |
|
|
reg rd;
|
| 93 |
|
|
|
| 94 |
|
|
assign ack_o = cyc_i & stb_i & cs_i;
|
| 95 |
|
|
assign txd = tx_data[0];
|
| 96 |
|
|
|
| 97 |
|
|
always @(posedge clk_i)
|
| 98 |
|
|
if (ack_o & we_i) fdo <= dat_i;
|
| 99 |
|
|
|
| 100 |
|
|
// set full / empty status
|
| 101 |
|
|
always @(posedge clk_i)
|
| 102 |
|
|
if (rst_i) empty <= 1;
|
| 103 |
|
|
else begin
|
| 104 |
|
|
if (ack_o & we_i) empty <= 0;
|
| 105 |
|
|
else if (rd) empty <= 1;
|
| 106 |
|
|
end
|
| 107 |
|
|
|
| 108 |
|
|
|
| 109 |
|
|
always @(posedge clk_i)
|
| 110 |
|
|
if (rst_i) begin
|
| 111 |
|
|
cnt <= 8'h00;
|
| 112 |
|
|
rd <= 0;
|
| 113 |
|
|
tx_data <= 10'h3FF;
|
| 114 |
|
|
end
|
| 115 |
|
|
else begin
|
| 116 |
|
|
|
| 117 |
|
|
rd <= 0;
|
| 118 |
|
|
|
| 119 |
|
|
if (baud16x_ce) begin
|
| 120 |
|
|
|
| 121 |
|
|
cnt <= cnt + 1;
|
| 122 |
|
|
// Load next data ?
|
| 123 |
|
|
if (cnt==8'h9F) begin
|
| 124 |
|
|
cnt <= 0;
|
| 125 |
|
|
if (!empty && cts) begin
|
| 126 |
|
|
tx_data <= {1'b1,fdo,1'b0};
|
| 127 |
|
|
rd <= 1;
|
| 128 |
|
|
end
|
| 129 |
|
|
end
|
| 130 |
|
|
// Shift the data out. LSB first.
|
| 131 |
|
|
else if (cnt[3:0]==4'hF)
|
| 132 |
|
|
tx_data <= {1'b1,tx_data[9:1]};
|
| 133 |
|
|
|
| 134 |
|
|
end
|
| 135 |
|
|
end
|
| 136 |
|
|
|
| 137 |
|
|
endmodule
|
