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[/] [rtftextcontroller/] [trunk/] [rtl/] [verilog/] [ParallelToSerial.v] - Blame information for rev 20

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/* ============================================================================
        2006,2007,2011  Robert T Finch
        robfinch@<remove>sympatico.ca
 
        ParallelToSerial.v
                Parallel to serial data converter (shift register).
 
    This source code is available for evaluation and validation purposes
    only. This copyright statement and disclaimer must remain present in
    the file.
 
 
        NO WARRANTY.
    THIS Work, IS PROVIDEDED "AS IS" WITH NO WARRANTIES OF ANY KIND, WHETHER
    EXPRESS OR IMPLIED. The user must assume the entire risk of using the
    Work.
 
    IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
    INCIDENTAL, CONSEQUENTIAL, OR PUNITIVE DAMAGES WHATSOEVER RELATING TO
    THE USE OF THIS WORK, OR YOUR RELATIONSHIP WITH THE AUTHOR.
 
    IN ADDITION, IN NO EVENT DOES THE AUTHOR AUTHORIZE YOU TO USE THE WORK
    IN APPLICATIONS OR SYSTEMS WHERE THE WORK'S FAILURE TO PERFORM CAN
    REASONABLY BE EXPECTED TO RESULT IN A SIGNIFICANT PHYSICAL INJURY, OR IN
    LOSS OF LIFE. ANY SUCH USE BY YOU IS ENTIRELY AT YOUR OWN RISK, AND YOU
    AGREE TO HOLD THE AUTHOR AND CONTRIBUTORS HARMLESS FROM ANY CLAIMS OR
    LOSSES RELATING TO SUCH UNAUTHORIZED USE.
 
 
        Webpack 9.1i xc3s1000-4ft256
        LUTs / slices / MHz
        block rams
 
============================================================================ */
 
module ParallelToSerial(rst, clk, ce, ld, qin, d, qh);
        parameter WID=8;
        input rst;                      // reset
        input clk;                      // clock
        input ce;                       // clock enable
        input ld;                       // load
        input qin;                      // serial shifting input
        input [WID:1] d;        // data to load
        output qh;                      // serial output
 
        reg [WID:1] q;
 
        always @(posedge clk)
                if (rst)
                        q <= 0;
                else if (ce) begin
                        if (ld)
                                q <= d;
                        else
                                q <= {q[WID-1:1],qin};
                end
 
        assign qh = q[WID];
 
endmodule

Line No.	Rev	Author	Line
1	3	robfinch	`/* ============================================================================`
2			`2006,2007,2011 Robert T Finch`
3			`robfinch@<remove>sympatico.ca`
4
5			`ParallelToSerial.v`
6			`Parallel to serial data converter (shift register).`
7
8			`This source code is available for evaluation and validation purposes`
9			`only. This copyright statement and disclaimer must remain present in`
10			`the file.`
11
12
13			`NO WARRANTY.`
14			`THIS Work, IS PROVIDEDED "AS IS" WITH NO WARRANTIES OF ANY KIND, WHETHER`
15			`EXPRESS OR IMPLIED. The user must assume the entire risk of using the`
16			`Work.`
17
18			`IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY`
19			`INCIDENTAL, CONSEQUENTIAL, OR PUNITIVE DAMAGES WHATSOEVER RELATING TO`
20			`THE USE OF THIS WORK, OR YOUR RELATIONSHIP WITH THE AUTHOR.`
21
22			`IN ADDITION, IN NO EVENT DOES THE AUTHOR AUTHORIZE YOU TO USE THE WORK`
23			`IN APPLICATIONS OR SYSTEMS WHERE THE WORK'S FAILURE TO PERFORM CAN`
24			`REASONABLY BE EXPECTED TO RESULT IN A SIGNIFICANT PHYSICAL INJURY, OR IN`
25			`LOSS OF LIFE. ANY SUCH USE BY YOU IS ENTIRELY AT YOUR OWN RISK, AND YOU`
26			`AGREE TO HOLD THE AUTHOR AND CONTRIBUTORS HARMLESS FROM ANY CLAIMS OR`
27			`LOSSES RELATING TO SUCH UNAUTHORIZED USE.`
28
29
30			`Webpack 9.1i xc3s1000-4ft256`
31			`LUTs / slices / MHz`
32			`block rams`
33
34			`============================================================================ */`
35
36			`module ParallelToSerial(rst, clk, ce, ld, qin, d, qh);`
37			`parameter WID=8;`
38			`input rst; // reset`
39			`input clk; // clock`
40			`input ce; // clock enable`
41			`input ld; // load`
42			`input qin; // serial shifting input`
43			`input [WID:1] d; // data to load`
44			`output qh; // serial output`
45
46			`reg [WID:1] q;`
47
48			`always @(posedge clk)`
49			`if (rst)`
50			`q <= 0;`
51			`else if (ce) begin`
52			`if (ld)`
53			`q <= d;`
54			`else`
55			`q <= {q[WID-1:1],qin};`
56			`end`
57
58			`assign qh = q[WID];`
59
60			`endmodule`

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[/] [rtftextcontroller/] [trunk/] [rtl/] [verilog/] [ParallelToSerial.v] - Blame information for rev 20