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[/] [rtftextcontroller/] [trunk/] [rtl/] [verilog/] [VT151.v] - Blame information for rev 21

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1 3 robfinch 
// (C) 2007  Robert T Finch
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// All Rights Reserved.
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//
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// 74LS151 mux
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// 8-to-1 mux with enable
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//
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// Webpack 9.1i  xc3s1000-4ft256
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//  slices /  LUTs / MHz
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module VT151(e_n, s, i0, i1, i2, i3, i4, i5, i6, i7, z, z_n);
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        parameter WID=1;
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        input e_n;
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        input [2:0] s;
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        input [WID:1] i0;
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        input [WID:1] i1;
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        input [WID:1] i2;
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        input [WID:1] i3;
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        input [WID:1] i4;
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        input [WID:1] i5;
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        input [WID:1] i6;
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        input [WID:1] i7;
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        output [WID:1] z;
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        output [WID:1] z_n;
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        reg [WID:1] z;
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        always @(e_n or s or i0 or i1 or i2 or i3 or i4 or i5 or i6 or i7)
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                case({e_n,s})
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                4'b0000:        z <= i0;
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                4'b0001:        z <= i1;
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                4'b0010:        z <= i2;
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                4'b0011:        z <= i3;
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                4'b0100:        z <= i4;
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                4'b0101:        z <= i5;
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                4'b0110:        z <= i6;
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                4'b0111:        z <= i7;
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                default:        z <= {WID{1'b0}};
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                endcase
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        assign z_n = !z;
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endmodule

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