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robfinch |
// ============================================================================
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// __
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// \\__/ o\ (C) 2018-2022 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \/_// robfinch@finitron.ca
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// ||
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//
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//
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// BSD 3-Clause License
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice, this
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// list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// ============================================================================
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//
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module rfTextCharRam(clk_i, cs_i, we_i, sel_i, adr_i, dat_i, dat_o, dot_clk_i, ce_i,
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fontAddress_i, char_code_i, maxScanpix_i, maxscanline_i, scanline_i, bmp_o);
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parameter pFontFile = "char_bitmaps_12x18.mem";
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input clk_i;
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input cs_i;
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input we_i;
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input [7:0] sel_i;
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input [15:3] adr_i;
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input [63:0] dat_i;
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output [63:0] dat_o;
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input dot_clk_i;
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input ce_i;
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input [15:0] fontAddress_i;
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input [12:0] char_code_i;
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input [5:0] maxScanpix_i;
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input [5:0] maxscanline_i;
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input [5:0] scanline_i;
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output reg [63:0] bmp_o;
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wire [63:0] memo;
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reg [15:0] rcc, rcc0, rcc1, rcc2, rcc3;
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reg [2:0] rcc200, rcc201, rcc202;
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reg [1:0] bndx;
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reg [63:0] bmp1;
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//reg [7:0] bmp [0:7];
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wire pe_cs;
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edge_det ued1 (.rst(1'b0), .clk(clk_i), .ce(1'b1), .i(cs_i), .pe(pe_cs), .ne(), .ee());
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reg [7:0] wea;
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always_comb
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wea <= {8{we_i}} & sel_i;
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// xpm_memory_tdpram: True Dual Port RAM
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// Xilinx Parameterized Macro, version 2020.2
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`ifdef VENDOR_XILINX
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xpm_memory_tdpram #(
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.ADDR_WIDTH_A(13),
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.ADDR_WIDTH_B(13),
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.AUTO_SLEEP_TIME(0),
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.BYTE_WRITE_WIDTH_A(8),
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.BYTE_WRITE_WIDTH_B(8),
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.CASCADE_HEIGHT(0),
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.CLOCKING_MODE("independent_clock"), // String
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.ECC_MODE("no_ecc"), // String
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.MEMORY_INIT_FILE(pFontFile), // String
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.MEMORY_INIT_PARAM(""), // String
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.MEMORY_OPTIMIZATION("true"), // String
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.MEMORY_PRIMITIVE("block"), // String
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.MEMORY_SIZE(524288),
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.MESSAGE_CONTROL(0),
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.READ_DATA_WIDTH_A(64),
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.READ_DATA_WIDTH_B(64),
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.READ_LATENCY_A(2),
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.READ_LATENCY_B(1),
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.READ_RESET_VALUE_A("0"), // String
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.READ_RESET_VALUE_B("0"), // String
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.RST_MODE_A("SYNC"), // String
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.RST_MODE_B("SYNC"), // String
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.SIM_ASSERT_CHK(0), // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
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.USE_EMBEDDED_CONSTRAINT(0), // DECIMAL
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.USE_MEM_INIT(1),
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.WAKEUP_TIME("disable_sleep"), // String
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.WRITE_DATA_WIDTH_A(64),
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.WRITE_DATA_WIDTH_B(64),
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.WRITE_MODE_A("no_change"), // String
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.WRITE_MODE_B("no_change") // String
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)
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xpm_memory_tdpram_inst (
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.dbiterra(), // 1-bit output: Status signal to indicate double bit error occurrence
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// on the data output of port A.
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.dbiterrb(), // 1-bit output: Status signal to indicate double bit error occurrence
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// on the data output of port A.
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.douta(dat_o), // READ_DATA_WIDTH_A-bit output: Data output for port A read operations.
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.doutb(memo), // READ_DATA_WIDTH_B-bit output: Data output for port B read operations.
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.sbiterra(), // 1-bit output: Status signal to indicate single bit error occurrence
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// on the data output of port A.
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.sbiterrb(), // 1-bit output: Status signal to indicate single bit error occurrence
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// on the data output of port B.
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.addra(adr_i), // ADDR_WIDTH_A-bit input: Address for port A write and read operations.
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.addrb(rcc3[15:3]), // ADDR_WIDTH_B-bit input: Address for port B write and read operations.
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.clka(clk_i), // 1-bit input: Clock signal for port A. Also clocks port B when
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// parameter CLOCKING_MODE is "common_clock".
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.clkb(~dot_clk_i), // 1-bit input: Clock signal for port B when parameter CLOCKING_MODE is
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// "independent_clock". Unused when parameter CLOCKING_MODE is
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// "common_clock".
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.dina(dat_i), // WRITE_DATA_WIDTH_A-bit input: Data input for port A write operations.
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.dinb(64'h0), // WRITE_DATA_WIDTH_B-bit input: Data input for port B write operations.
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.ena(cs_i), // 1-bit input: Memory enable signal for port A. Must be high on clock
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// cycles when read or write operations are initiated. Pipelined
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// internally.
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.enb(~bndx[1]), // 1-bit input: Memory enable signal for port B. Must be high on clock
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// cycles when read or write operations are initiated. Pipelined
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// internally.
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.injectdbiterra(1'b0), // 1-bit input: Controls double bit error injection on input data when
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// ECC enabled (Error injection capability is not available in
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// "decode_only" mode).
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.injectdbiterrb(1'b0), // 1-bit input: Controls double bit error injection on input data when
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// ECC enabled (Error injection capability is not available in
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// "decode_only" mode).
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.injectsbiterra(1'b0), // 1-bit input: Controls single bit error injection on input data when
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// ECC enabled (Error injection capability is not available in
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// "decode_only" mode).
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.injectsbiterrb(1'b0), // 1-bit input: Controls single bit error injection on input data when
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// ECC enabled (Error injection capability is not available in
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// "decode_only" mode).
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.regcea(cs_i), // 1-bit input: Clock Enable for the last register stage on the output
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// data path.
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.regceb(1'b1), // 1-bit input: Clock Enable for the last register stage on the output
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// data path.
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.rsta(1'b0), // 1-bit input: Reset signal for the final port A output register stage.
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// Synchronously resets output port douta to the value specified by
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// parameter READ_RESET_VALUE_A.
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.rstb(1'b0), // 1-bit input: Reset signal for the final port B output register stage.
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// Synchronously resets output port doutb to the value specified by
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// parameter READ_RESET_VALUE_B.
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.sleep(1'b0), // 1-bit input: sleep signal to enable the dynamic power saving feature.
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.wea(wea), // WRITE_DATA_WIDTH_A/BYTE_WRITE_WIDTH_A-bit input: Write enable vector
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// for port A input data port dina. 1 bit wide when word-wide writes are
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// used. In byte-wide write configurations, each bit controls the
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// writing one byte of dina to address addra. For example, to
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// synchronously write only bits [15-8] of dina when WRITE_DATA_WIDTH_A
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// is 32, wea would be 4'b0010.
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.web(8'h00) // WRITE_DATA_WIDTH_B/BYTE_WRITE_WIDTH_B-bit input: Write enable vector
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// for port B input data port dinb. 1 bit wide when word-wide writes are
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// used. In byte-wide write configurations, each bit controls the
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// writing one byte of dinb to address addrb. For example, to
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// synchronously write only bits [15-8] of dinb when WRITE_DATA_WIDTH_B
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// is 32, web would be 4'b0010.
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);
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`elsif VENDOR_ALTERA
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genvar g;
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generate begin : gAlteraRAM
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for (g = 0; g < 8; g = g + 1) begin
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ALTSYNCRAM #(
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.OPERATION_MODE("DUAL_PORT"),
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.WIDTH_A(8),
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.WIDTHAD_A(13),
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.WIDTH_B(8),
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.WIDTHAD_B(13),
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.READ_DURING_WRITE_MIXED_PORTS("DONT_CARE")
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) charram0 (
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.clock0(clk_i),
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.clock1(clk_i),
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// Write port
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.wren_a(we_i & sel_i[g]),
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.address_a(adr_i),
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.data_a(dat_i[g*8+7:g*8]),
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.q_a(),
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// Read port
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.rden_b(1'b1),
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.address_b(adr_i),
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.q_b(dat_o[g*8+7:g*8])
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);
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ALTSYNCRAM #(
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.OPERATION_MODE("DUAL_PORT"),
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.WIDTH_A(8),
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.WIDTHAD_A(13),
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.WIDTH_B(8),
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.WIDTHAD_B(13),
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.READ_DURING_WRITE_MIXED_PORTS("DONT_CARE")
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) charram1 (
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.clock0(clk_i),
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.clock1(~dot_clk_i),
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// Write port
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.wren_a(we_i & sel_i[g]),
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.address_a(adr_i),
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.data_a(dat_i[g*8+7:g*8]),
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.q_a(),
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// Read port
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.rden_b(1'b1),
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.address_b(rcc3[15:3]),
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.q_b(memo[g*8+7:g*8])
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);
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end
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end
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endgenerate
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`else
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/* ToDo: implement the rest of this */
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reg [63:0] mem [0:8191];
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always_ff @(posedge clk_i)
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begin
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end
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always_comb
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begin
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$display("No RAM vendor selected.");
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$finish();
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end
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`endif
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reg [3:0] scan_width; // scan width in bytes rounded up
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always_comb
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scan_width = maxScanpix_i[5:3] + |maxScanpix_i[2:0];
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reg [9:0] char_size; // character size in bytes
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always_comb
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char_size = maxscanline_i * scan_width;
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reg [6:0] char_size8; // character size in octa-bytes
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always_comb
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char_size8 = char_size[9:3] + |char_size[2:0];
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// Char code is already delated two clocks relative to ce
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// Assume that characters are always going to be at least four clocks wide.
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// Clock #0
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always_ff @(posedge dot_clk_i)
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if (ce_i)
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rcc <= char_code_i*{char_size8,3'b0}+scanline_i*scan_width;
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// Provide some pipeline stages for the previous multiplies and adds
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// Clock #1
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always_ff @(posedge dot_clk_i)
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rcc0 <= rcc;
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always_ff @(posedge dot_clk_i)
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rcc1 <= rcc0;
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always_ff @(posedge dot_clk_i)
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rcc2 <= rcc1;
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// Clock #2
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always_ff @(posedge dot_clk_i)
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if (ce_i) begin
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rcc3 <= {fontAddress_i[15:3],3'b0}+rcc2;
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bndx <= 'd0;
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end
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else begin
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case(bndx)
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2'd0: bmp1 <= memo >> {rcc3[2:0],3'b0}; // right half
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2'd1: bmp1 <= (memo << {4'd8-rcc3[2:0],3'b0}) | bmp1; // left half
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default: ;
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endcase
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if (bndx < 2'd2)
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bndx <= bndx + 2'd1;
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rcc3 <= rcc3 + 4'd8;
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/*
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if (bndx[2:0] <= maxScanpix_i[5:3]) begin
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bmp[bndx[2:0]] <= memo8;
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rcc1 <= rcc1 + 1'd1;
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bndx <= bndx + 1'd1;
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end
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*/
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end
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always @(posedge dot_clk_i)
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if (ce_i)
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bmp_o <= bmp1;//{bmp[7],bmp[6],bmp[5],bmp[4],bmp[3],bmp[2],bmp[1],bmp[0]};
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endmodule
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