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[/] [rtftextcontroller/] [trunk/] [rtl/] [verilog/] [rtfTextController3.v] - Blame information for rev 26

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1 22 robfinch
`timescale 1ns / 1ps
2 25 robfinch
// ============================================================================
3 22 robfinch
//        __
4
//   \\__/ o\    (C) 2006-2014  Robert Finch, Stratford
5
//    \  __ /    All rights reserved.
6
//     \/_//     robfinch<remove>@finitron.ca
7
//       ||
8 25 robfinch
//
9
//      rtfTextController3.v
10
//              text controller
11
//
12
// This source file is free software: you can redistribute it and/or modify 
13
// it under the terms of the GNU Lesser General Public License as published 
14
// by the Free Software Foundation, either version 3 of the License, or     
15
// (at your option) any later version.                                      
16
//                                                                          
17
// This source file is distributed in the hope that it will be useful,      
18
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
19
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
20
// GNU General Public License for more details.                             
21
//                                                                          
22
// You should have received a copy of the GNU General Public License        
23
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
24
//                                                                          
25
//
26
//      Text Controller
27
//
28
//      FEATURES
29
//
30
//      This core requires an external timing generator to provide horizontal
31
//      and vertical sync signals, but otherwise can be used as a display
32
//  controller on it's own. However, this core may also be embedded within
33
//  another core such as a VGA controller.
34
//
35
//      Window positions are referenced to the rising edge of the vertical and
36
//      horizontal sync pulses.
37
//
38
//      The core includes an embedded dual port RAM to hold the screen
39
//      characters.
40
//
41
//
42
//--------------------------------------------------------------------
43
// Registers
44
//
45
//      00 -         nnnnnnnn  number of columns (horizontal displayed number of characters)
46
//      01 -         nnnnnnnn  number of rows    (vertical displayed number of characters)
47
//      02 -       n nnnnnnnn  window left       (horizontal sync position - reference for left edge of displayed)
48
//      03 -       n nnnnnnnn  window top        (vertical sync position - reference for the top edge of displayed)
49
//      04 -         ---nnnnn  maximum scan line (char ROM max value is 7)
50
//              05 -         hhhhwwww  pixel size, hhhh=height,wwww=width
51
//      07 -       n nnnnnnnn  color code for transparent background
52
//      08 -         -BPnnnnn  cursor start / blink control
53
//                             BP: 00=no blink
54
//                             BP: 01=no display
55
//                             BP: 10=1/16 field rate blink
56
//                             BP: 11=1/32 field rate blink
57
//      09 -        ----nnnnn  cursor end
58
//      10 - aaaaaaaa aaaaaaaaa  start address (index into display memory)
59
//      11 - aaaaaaaa aaaaaaaaa  cursor position
60
//      12 - aaaaaaaa aaaaaaaaa  light pen position
61
//--------------------------------------------------------------------
62
//
63
// ============================================================================
64
 
65
module rtfTextController3(
66
        rst_i, clk_i,
67
        cyc_i, stb_i, ack_o, we_i, adr_i, dat_i, dat_o,
68
        lp, curpos,
69
        vclk, hsync, vsync, blank, border, rgbIn, rgbOut
70
);
71
parameter num = 4'd1;
72
parameter COLS = 12'd84;
73 22 robfinch
parameter ROWS = 12'd31;
74
parameter pTextAddress = 32'hFFD00000;
75
parameter pBitmapAddress = 32'hFFD20000;
76 25 robfinch
parameter pRegAddress = 32'hFFDA0000;
77 22 robfinch
 
78 25 robfinch
// Syscon
79
input  rst_i;                   // reset
80
input  clk_i;                   // clock
81
 
82
// Slave signals
83
input  cyc_i;                   // cycle valid
84
input  stb_i;                   // data strobe
85
output ack_o;                   // transfer acknowledge
86
input  we_i;                    // write
87
input  [31:0] adr_i;     // address
88
input  [31:0] dat_i;     // data input
89
output [31:0] dat_o;     // data output
90
reg    [31:0] dat_o;
91
 
92
//
93
input lp;                               // light pen
94
input [15:0] curpos;     // cursor position
95
 
96
// Video signals
97
input vclk;                             // video dot clock
98
input hsync;                    // end of scan line
99
input vsync;                    // end of frame
100
input blank;                    // blanking signal
101
input border;                   // border area
102
input [24:0] rgbIn;              // input pixel stream
103
output reg [24:0] rgbOut;        // output pixel stream
104
 
105
 
106
reg [23:0] bkColor24;    // background color
107
reg [23:0] fgColor24;    // foreground color
108
wire [23:0] tcColor24;   // transparent color
109
 
110
wire pix;                               // pixel value from character generator 1=on,0=off
111
 
112
reg [15:0] rego;
113
reg [11:0] windowTop;
114
reg [11:0] windowLeft;
115
reg [11:0] numCols;
116 22 robfinch
reg [11:0] numRows;
117 25 robfinch
reg [11:0] charOutDelay;
118
reg [ 1:0] mode;
119
reg [ 4:0] maxScanline;
120
reg [ 4:0] maxScanpix;
121
reg [ 4:0] cursorStart, cursorEnd;
122 22 robfinch
reg [15:0] cursorPos;
123 25 robfinch
reg [1:0] cursorType;
124
reg [15:0] startAddress;
125
reg [ 2:0] rBlink;
126
reg [ 3:0] bdrColorReg;
127
reg [ 3:0] pixelWidth;   // horizontal pixel width in clock cycles
128
reg [ 3:0] pixelHeight;  // vertical pixel height in scan lines
129
 
130
wire [11:0] hctr;                // horizontal reference counter (counts clocks since hSync)
131
wire [11:0] scanline;    // scan line
132
wire [11:0] row;         // vertical reference counter (counts rows since vSync)
133
wire [11:0] col;         // horizontal column
134
reg  [ 4:0] rowscan;     // scan line within row
135
wire nxt_row;                   // when to increment the row counter
136
wire nxt_col;                   // when to increment the column counter
137
wire [ 5:0] bcnt;                // blink timing counter
138
wire blink;
139
reg  iblank;
140
 
141
wire nhp;                               // next horizontal pixel
142
wire ld_shft = nxt_col & nhp;
143
 
144
 
145
// display and timing signals
146
reg [15:0] txtAddr;              // index into memory
147
reg [15:0] penAddr;
148
wire [8:0] txtOut;               // character code
149
wire [8:0] charOut;              // character ROM output
150
wire [8:0] txtBkColor;   // background color code
151
wire [8:0] txtFgColor;   // foreground color code
152 22 robfinch
reg  [8:0] txtTcCode;    // transparent color code
153 25 robfinch
reg  bgt;
154 22 robfinch
 
155 25 robfinch
wire [27:0] tdat_o;
156
wire [8:0] chdat_o;
157
 
158
wire [2:0] scanindex = scanline[2:0];
159
 
160
 
161
//--------------------------------------------------------------------
162
// Address Decoding
163
// I/O range Dx
164
//--------------------------------------------------------------------
165
wire cs_text = cyc_i && stb_i && (adr_i[31:16]==pTextAddress[31:16]);
166
wire cs_rom  = cyc_i && stb_i && (adr_i[31:16]==pBitmapAddress[31:16]);
167
wire cs_reg  = cyc_i && stb_i && (adr_i[31: 6]==pRegAddress[31:6]);
168
wire cs_any = cs_text|cs_rom|cs_reg;
169
 assign tdat_o[9] = 1'b0;
170
 
171
// Register outputs
172 22 robfinch
always @(posedge clk_i)
173 25 robfinch
        if (cs_text) dat_o <= {4'd0,tdat_o};
174
        else if (cs_rom) dat_o <= {23'd0,chdat_o};
175
        else if (cs_reg) dat_o <= {16'd0,rego};
176
        else dat_o <= 32'h0000;
177 22 robfinch
 
178
//always @(posedge clk_i)
179
//      if (cs_text) begin
180
//              $display("TC WRite: %h %h", adr_i, dat_i);
181
//              $stop;
182
//      end
183 25 robfinch
 
184
//--------------------------------------------------------------------
185
// Video Memory
186
//--------------------------------------------------------------------
187
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
188
// Address Calculation:
189
//  - Simple: the row times the number of  cols plus the col plus the
190
//    base screen address
191
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
192
 
193
wire [17:0] rowcol = row * numCols;
194
always @(posedge vclk)
195
        txtAddr <= startAddress + rowcol[15:0] + col;
196
 
197
// text screen RAM
198
syncRam4kx9_1rw1r textRam0
199
(
200
        .wclk(clk_i),
201
        .wadr(adr_i[13:2]),
202
        .i(dat_i[8:0]),
203
        .wo(tdat_o[8:0]),
204
        .wce(cs_text),
205
        .we(we_i),
206
        .wrst(1'b0),
207
 
208
        .rclk(vclk),
209
        .radr(txtAddr[11:0]),
210
        .o(txtOut),
211
        .rce(ld_shft),
212
        .rrst(1'b0)
213
);
214
 
215
// screen attribute RAM
216
syncRam4kx9_1rw1r fgColorRam
217
(
218
        .wclk(clk_i),
219
        .wadr(adr_i[13:2]),
220
        .i(dat_i[18:10]),
221
        .wo(tdat_o[18:10]),
222
        .wce(cs_text),
223
        .we(we_i),
224
        .wrst(1'b0),
225
 
226
        .rclk(vclk),
227
        .radr(txtAddr[11:0]),
228
        .o(txtFgColor),
229
        .rce(ld_shft),
230
        .rrst(1'b0)
231
);
232
 
233
// screen attribute RAM
234
syncRam4kx9_1rw1r bkColorRam
235
(
236
        .wclk(clk_i),
237
        .wadr(adr_i[13:2]),
238
        .i(dat_i[27:19]),
239
        .wo(tdat_o[27:19]),
240
        .wce(cs_text),
241
        .we(we_i),
242
        .wrst(1'b0),
243
 
244
        .rclk(vclk),
245
        .radr(txtAddr[11:0]),
246
        .o(txtBkColor),
247
        .rce(ld_shft),
248
        .rrst(1'b0)
249
);
250
 
251
 
252
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
253
// Character bitmap ROM
254
// - room for 512 characters
255
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
256
syncRam4kx9_1rw1r charRam0
257
(
258
        .wclk(clk_i),
259
        .wadr(adr_i[13:2]),
260
        .i(dat_i),
261
        .wo(chdat_o),
262
        .wce(cs_rom),
263
        .we(1'b0),//we_i),
264
        .wrst(1'b0),
265
 
266
        .rclk(vclk),
267
        .radr({txtOut,rowscan[2:0]}),
268
        .o(charOut),
269
        .rce(ld_shft),
270
        .rrst(1'b0)
271
);
272
 
273
 
274
// pipeline delay - sync color with character bitmap output
275
reg [8:0] txtBkCode1;
276
reg [8:0] txtFgCode1;
277
always @(posedge vclk)
278
        if (nhp & ld_shft) txtBkCode1 <= txtBkColor;
279
always @(posedge vclk)
280
        if (nhp & ld_shft) txtFgCode1 <= txtFgColor;
281
 
282
//--------------------------------------------------------------------
283
// bus interfacing
284
// - there is a two cycle latency for reads, an ack is generated
285
//   after the synchronous RAM read
286
// - writes can be acknowledged right away.
287
//--------------------------------------------------------------------
288
reg ramRdy,ramRdy1;
289 22 robfinch
always @(posedge clk_i)
290
begin
291
        ramRdy1 <= cs_any;
292
        ramRdy <= ramRdy1 & cs_any;
293 25 robfinch
end
294
 
295
assign ack_o = cs_any ? (we_i ? 1'b1 : ramRdy) : 1'b0;
296
 
297
 
298
//--------------------------------------------------------------------
299
// Registers
300
//
301
// RW   00 -         nnnnnnnn  number of columns (horizontal displayed number of characters)
302
// RW   01 -         nnnnnnnn  number of rows    (vertical displayed number of characters)
303
//  W   02 -       n nnnnnnnn  window left       (horizontal sync position - reference for left edge of displayed)
304
//  W   03 -       n nnnnnnnn  window top        (vertical sync position - reference for the top edge of displayed)
305
//  W   04 -         ---nnnnn  maximum scan line (char ROM max value is 7)
306 22 robfinch
//      W       05 -         hhhhwwww  pixel size, hhhh=height,wwww=width
307 25 robfinch
//  W   07 -       n nnnnnnnn  transparent color
308
//  W   08 -         -BPnnnnn  cursor start / blink control
309
//                             BP: 00=no blink
310
//                             BP: 01=no display
311
//                             BP: 10=1/16 field rate blink
312
//                             BP: 11=1/32 field rate blink
313
//  W   09 -        ----nnnnn  cursor end
314
//  W   10 - aaaaaaaa aaaaaaaaa  start address (index into display memory)
315
//  W   11 - aaaaaaaa aaaaaaaaa  cursor position
316
//  R   12 - aaaaaaaa aaaaaaaaa  light pen position
317
//--------------------------------------------------------------------
318
 
319
//--------------------------------------------------------------------
320
// Light Pen
321
//--------------------------------------------------------------------
322
wire lpe;
323
edge_det u1 (.rst(rst_i), .clk(clk_i), .ce(1'b1), .i(lp), .pe(lpe), .ne(), .ee() );
324
 
325
always @(posedge clk_i)
326
        if (rst_i)
327
                penAddr <= 32'h0000_0000;
328
        else begin
329
                if (lpe)
330
                        penAddr <= txtAddr;
331
        end
332
 
333
 
334
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
335
// Register read port
336
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
337
always @(cs_reg or cursorPos or penAddr or adr_i or numCols or numRows)
338
        if (cs_reg) begin
339
                case(adr_i[5:2])
340
                4'd0:           rego <= numCols;
341
                4'd1:           rego <= numRows;
342
                4'd11:          rego <= cursorPos;
343
                4'd12:          rego <= penAddr;
344
                default:        rego <= 16'h0000;
345
                endcase
346
        end
347
        else
348
                rego <= 16'h0000;
349
 
350
 
351
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
352
// Register write port
353
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
354
 
355
reg interlace;
356
always @(posedge clk_i)
357
        if (rst_i) begin
358
// 104x63
359
/*
360
                windowTop    <= 12'd26;
361
                windowLeft   <= 12'd260;
362
                pixelWidth   <= 4'd0;
363
                pixelHeight  <= 4'd1;           // 525 pixels (408 with border)
364
*/
365 22 robfinch
// 52x31
366
/*
367 25 robfinch
                // 84x47
368
                windowTop    <= 12'd16;
369
                windowLeft   <= 12'd90;
370
                pixelWidth   <= 4'd1;           // 681 pixels
371
                pixelHeight  <= 4'd1;           // 384 pixels
372
*/
373
                // 56x31
374
                if (num==4'd1) begin
375
            windowTop    <= 12'd16;//12'd16;
376
            windowLeft   <= 12'h66;//12'd86;
377
            pixelWidth   <= 4'd1;               // 680 pixels
378
            pixelHeight  <= 4'd2;               // 256 pixels
379
            numCols      <= COLS;
380
            numRows      <= ROWS;
381
            maxScanline  <= 5'd7;
382
            maxScanpix   <= 5'd7;
383
            rBlink       <= 3'b111;             // 01 = non display
384
            startAddress <= 16'h0000;
385
            cursorStart  <= 5'd00;
386
            cursorEnd    <= 5'd31;
387
            cursorPos    <= 16'h0003;
388
            cursorType   <= 2'b00;
389
            txtTcCode    <= 9'h1ff;
390
            charOutDelay <= 12'd2;
391
                end
392
                else if (num==4'd2) begin
393
            windowTop    <= 12'd64;//12'd16;
394
            windowLeft   <= 12'h376;//12'd86;
395
            pixelWidth   <= 4'd0;        // 680 pixels
396
            pixelHeight  <= 4'd1;        // 256 pixels
397
            numCols      <= 40;
398
            numRows      <= 25;
399
            maxScanline  <= 5'd7;
400
            maxScanpix   <= 5'd7;
401
            rBlink       <= 3'b111;        // 01 = non display
402
            startAddress <= 16'h0000;
403
            cursorStart  <= 5'd00;
404
            cursorEnd    <= 5'd31;
405
            cursorPos    <= 16'h0003;
406
            cursorType   <= 2'b00;
407
            txtTcCode    <= 9'h1ff;
408
            charOutDelay <= 12'd2;
409
                end
410
        end
411
        else begin
412
 
413
                if (cs_reg & we_i) begin        // register write ?
414
                        $display("TC Write: r%d=%h", adr_i[5:2], dat_i);
415
                        case(adr_i[5:2])
416 22 robfinch
                        4'd00:  begin
417
                                        numCols    <= dat_i[15:0];               // horizontal displayed
418
                                        charOutDelay <= dat_i[31:16];
419 25 robfinch
                                        end
420
                        4'd01:  numRows    <= dat_i;
421
                        4'd02:  windowLeft <= dat_i[11:0];
422
                        4'd03:  windowTop  <= dat_i[11:0];               // vertical sync position
423
                        4'd04:  maxScanline <= dat_i[4:0];
424
                        4'd05:  begin
425
                                        pixelHeight <= dat_i[7:4];
426
                                        pixelWidth  <= dat_i[3:0];       // horizontal pixel width
427
                                        end
428
                        4'd07:  txtTcCode   <= dat_i[8:0];
429
                        4'd08:  begin
430
                                        cursorStart <= dat_i[4:0];       // scan line sursor starts on
431 22 robfinch
                                        rBlink      <= dat_i[7:5];
432 25 robfinch
                                        cursorType  <= dat_i[9:8];
433
                                        end
434
                        4'd09:  cursorEnd   <= dat_i[4:0];       // scan line cursor ends on
435
                        4'd10:  startAddress <= dat_i;
436
                        4'd11:  cursorPos <= dat_i[15:0];
437
                        default: ;
438
                        endcase
439
                end
440
        end
441
 
442
 
443
//--------------------------------------------------------------------
444
//--------------------------------------------------------------------
445
 
446
// "Box" cursor bitmap
447
reg [7:0] curout;
448
always @(scanindex or cursorType)
449 22 robfinch
        case({cursorType,scanindex})
450 25 robfinch
        // Box cursor
451
        5'b00_000:      curout = 8'b11111111;
452
        5'b00_001:      curout = 8'b10000001;
453
        5'b00_010:      curout = 8'b10000001;
454
        5'b00_011:      curout = 8'b10000001;
455
        5'b00_100:      curout = 8'b10000001;
456
        5'b00_101:      curout = 8'b10000001;
457
        5'b00_110:      curout = 8'b10011001;
458
        5'b00_111:      curout = 8'b11111111;
459 22 robfinch
        // vertical bar cursor
460 25 robfinch
        5'b01_000:      curout = 8'b11000000;
461
        5'b01_001:      curout = 8'b10000000;
462
        5'b01_010:      curout = 8'b10000000;
463
        5'b01_011:      curout = 8'b10000000;
464
        5'b01_100:      curout = 8'b10000000;
465
        5'b01_101:      curout = 8'b10000000;
466
        5'b01_110:      curout = 8'b10000000;
467
        5'b01_111:      curout = 8'b11000000;
468 22 robfinch
        // underline cursor
469 25 robfinch
        5'b10_000:      curout = 8'b00000000;
470
        5'b10_001:      curout = 8'b00000000;
471
        5'b10_010:      curout = 8'b00000000;
472
        5'b10_011:      curout = 8'b00000000;
473
        5'b10_100:      curout = 8'b00000000;
474
        5'b10_101:      curout = 8'b00000000;
475
        5'b10_110:      curout = 8'b00000000;
476
        5'b10_111:      curout = 8'b11111111;
477 22 robfinch
        // Asterisk
478 25 robfinch
        5'b11_000:      curout = 8'b00000000;
479
        5'b11_001:      curout = 8'b00000000;
480
        5'b11_010:      curout = 8'b00100100;
481
        5'b11_011:      curout = 8'b00011000;
482
        5'b11_100:      curout = 8'b01111110;
483
        5'b11_101:      curout = 8'b00011000;
484
        5'b11_110:      curout = 8'b00100100;
485
        5'b11_111:      curout = 8'b00000000;
486
        endcase
487 22 robfinch
 
488 25 robfinch
 
489
//-------------------------------------------------------------
490
// Video Stuff
491
//-------------------------------------------------------------
492
 
493 22 robfinch
wire pe_hsync;
494
wire pe_vsync;
495
edge_det edh1
496
(
497
        .rst(rst_i),
498
        .clk(vclk),
499
        .ce(1'b1),
500
        .i(hsync),
501
        .pe(pe_hsync),
502
        .ne(),
503
        .ee()
504
);
505
 
506
edge_det edv1
507
(
508
        .rst(rst_i),
509
        .clk(vclk),
510
        .ce(1'b1),
511
        .i(vsync),
512
        .pe(pe_vsync),
513
        .ne(),
514
        .ee()
515
);
516
 
517 25 robfinch
// Horizontal counter:
518
//
519
HVCounter uhv1
520
(
521
        .rst(rst_i),
522
        .vclk(vclk),
523
        .pixcce(1'b1),
524
        .sync(hsync),
525
        .cnt_offs(windowLeft),
526
        .pixsz(pixelWidth),
527
        .maxpix(maxScanpix),
528
        .nxt_pix(nhp),
529
        .pos(col),
530
        .nxt_pos(nxt_col),
531
        .ctr(hctr)
532
);
533
 
534
 
535
// Vertical counter:
536
//
537
HVCounter uhv2
538
(
539
        .rst(rst_i),
540
        .vclk(vclk),
541
        .pixcce(pe_hsync),
542
        .sync(vsync),
543
        .cnt_offs(windowTop),
544
        .pixsz(pixelHeight),
545
        .maxpix(maxScanline),
546
        .nxt_pix(nvp),
547
        .pos(row),
548
        .nxt_pos(nxt_row),
549
        .ctr(scanline)
550
);
551
 
552
always @(posedge vclk)
553
        rowscan <= scanline - row * (maxScanline+1);
554
 
555
 
556
// Blink counter
557
//
558
VT163 #(6) ub1
559
(
560
        .clk(vclk),
561
        .clr_n(!rst_i),
562
        .ent(pe_vsync),
563
        .enp(1'b1),
564
        .ld_n(1'b1),
565
        .d(6'd0),
566 22 robfinch
        .q(bcnt),
567 25 robfinch
        .rco()
568
);
569
 
570
wire blink_en = (cursorPos+2==txtAddr) && (scanline[4:0] >= cursorStart) && (scanline[4:0] <= cursorEnd);
571
 
572
VT151 ub2
573
(
574
        .e_n(!blink_en),
575
        .s(rBlink),
576
        .i0(1'b1), .i1(1'b0), .i2(bcnt[4]), .i3(bcnt[5]),
577
        .i4(1'b1), .i5(1'b0), .i6(bcnt[4]), .i7(bcnt[5]),
578
        .z(blink),
579
        .z_n()
580
);
581
 
582 22 robfinch
always @(posedge vclk)
583
        if (nhp & ld_shft)
584
                bkColor24 <= {txtBkCode1[8:6],5'h10,txtBkCode1[5:3],5'h10,txtBkCode1[2:0],5'h10};
585
always @(posedge vclk)
586
        if (nhp & ld_shft)
587
                fgColor24 <= {txtFgCode1[8:6],5'h10,txtFgCode1[5:3],5'h10,txtFgCode1[2:0],5'h10};
588
 
589
always @(posedge vclk)
590
        if (nhp & ld_shft)
591
                bgt <= txtBkCode1==txtTcCode;
592 25 robfinch
 
593
 
594
// Convert character bitmap to pixels
595
// For convenience, the character bitmap data in the ROM is in the
596
// opposite bit order to what's needed for the display. The following
597
// just alters the order without adding any hardware.
598
//
599
wire [7:0] charRev = {
600
        charOut[0],
601
        charOut[1],
602
        charOut[2],
603
        charOut[3],
604
        charOut[4],
605
        charOut[5],
606
        charOut[6],
607
        charOut[7]
608
};
609
 
610
wire [7:0] charout1 = blink ? (charRev ^ curout) : charRev;
611
 
612
// Convert parallel to serial
613
ParallelToSerial ups1
614
(
615
        .rst(rst_i),
616
        .clk(vclk),
617
        .ce(nhp),
618
        .ld(ld_shft),
619
        .qin(1'b0),
620
        .d(charout1),
621
        .qh(pix)
622
);
623
 
624
 
625
// Pipelining Effect:
626 22 robfinch
// - character output is delayed by 2 or 3 character times relative to the video counters
627 25 robfinch
//   depending on the resolution selected
628
// - this means we must adapt the blanking signal by shifting the blanking window
629
//   two or three character times.
630
wire bpix = hctr[1] ^ scanline[4];// ^ blink;
631
always @(posedge vclk)
632
        if (nhp)
633
                iblank <= (row >= numRows) || (col >= numCols + charOutDelay) || (col < charOutDelay);
634
 
635
 
636
// Choose between input RGB and controller generated RGB
637
// Select between foreground and background colours.
638
always @(posedge vclk)
639
        if (nhp) begin
640
                casex({blank,iblank,border,bpix,pix})
641
                5'b1xxxx:       rgbOut <= 25'h0000000;
642
                5'b01xxx:       rgbOut <= rgbIn;
643
                5'b0010x:       rgbOut <= 24'hBF2020;
644
                5'b0011x:       rgbOut <= 24'hDFDFDF;
645
                5'b000x0:       rgbOut <= bgt ? rgbIn : bkColor24;
646
                5'b000x1:       rgbOut <= fgColor24;
647
                default:        rgbOut <= rgbIn;
648
                endcase
649
        end
650
 
651
endmodule
652
 

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