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[/] [rtl/] [bench/] [tb_store_unit.v] - Blame information for rev 11

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//////////////////////////////////////////////////////////////////////////////////
// Engineer: Rafael de Oliveira Calçada (rafaelcalcada@gmail.com)
// 
// Create Date: 02.06.2020 16:03:55
// Module Name: tb_store_unit
// Project Name: Steel Core
// Description: Store Unit testbench
// 
// Dependencies: globals.vh
//               store_unit.v
// 
// Version 0.01
// 
//////////////////////////////////////////////////////////////////////////////////
 
/*********************************************************************************
 
MIT License
 
Copyright (c) 2020 Rafael de Oliveira Calçada
 
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
 
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
 
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
 
********************************************************************************/
 
`timescale 1ns / 1ps
`include "../globals.vh"
 
 
module tb_store_unit();
 
    reg [2:0] FUNCT3;
    reg [31:0] IADDER_OUT;
    reg [31:0] RS2;
    reg MEM_WR_REQ;
    wire [31:0] DATA_OUT;
    wire [31:0] D_ADDR;
    wire [3:0] WR_MASK;
    wire WR_REQ;
 
    store_unit dut(
 
        .FUNCT3(FUNCT3[1:0]),
        .IADDER_OUT(IADDER_OUT),
        .RS2(RS2),
        .MEM_WR_REQ(MEM_WR_REQ),
        .DATA_OUT(DATA_OUT),
        .D_ADDR(D_ADDR),
        .WR_MASK(WR_MASK),
        .WR_REQ(WR_REQ)
 
    );
 
    integer i;
 
    initial
    begin
 
        FUNCT3 = `FUNCT3_BYTE;
        RS2 = $random;
        MEM_WR_REQ = 1'b0;
 
        $display("Testing D_ADDR generation...");
 
        for(i = 0; i < 20; i=i+1)
        begin
 
            IADDER_OUT = $random;
 
            #10;
 
            if(D_ADDR != {IADDER_OUT[31:2], 2'b00})
            begin
                $display("FAIL. Check the results.");
                $finish;
            end
 
        end
 
        $display("D_ADDR generation OK.");
 
        $display("Testing SB signals generation...");
 
        FUNCT3 = `FUNCT3_BYTE;
        RS2 = $random;
        MEM_WR_REQ = 1'b1;
        IADDER_OUT[1:0] = 2'b00;
 
        #10;
 
        if(DATA_OUT != {24'b0, RS2[7:0]})
        begin
            $display("FAIL. Check the results.");
            $finish;
        end
        if(WR_REQ != 1'b1)
        begin
            $display("FAIL. Check the results.");
            $finish;
        end
        if(WR_MASK != 4'b0001)
        begin
            $display("FAIL. Check the results.");
            $finish;
        end
 
        FUNCT3 = `FUNCT3_BYTE;
        RS2 = $random;
        MEM_WR_REQ = 1'b1;
        IADDER_OUT[1:0] = 2'b01;
 
        #10;
 
        if(DATA_OUT != {16'b0, RS2[7:0], 8'b0})
        begin
            $display("FAIL. Check the results.");
            $finish;
        end
        if(WR_REQ != 1'b1)
        begin
            $display("FAIL. Check the results.");
            $finish;
        end
        if(WR_MASK != 4'b0010)
        begin
            $display("FAIL. Check the results.");
            $finish;
        end
 
        FUNCT3 = `FUNCT3_BYTE;
        RS2 = $random;
        MEM_WR_REQ = 1'b1;
        IADDER_OUT[1:0] = 2'b10;
 
        #10;
 
        if(DATA_OUT != {8'b0, RS2[7:0], 16'b0})
        begin
            $display("FAIL. Check the results.");
            $finish;
        end
        if(WR_REQ != 1'b1)
        begin
            $display("FAIL. Check the results.");
            $finish;
        end
        if(WR_MASK != 4'b0100)
        begin
            $display("FAIL. Check the results.");
            $finish;
        end
 
        FUNCT3 = `FUNCT3_BYTE;
        RS2 = $random;
        MEM_WR_REQ = 1'b1;
        IADDER_OUT[1:0] = 2'b11;
 
        #10;
 
        if(DATA_OUT != {RS2[7:0], 24'b0})
        begin
            $display("FAIL. Check the results.");
            $finish;
        end
        if(WR_REQ != 1'b1)
        begin
            $display("FAIL. Check the results.");
            $finish;
        end
        if(WR_MASK != 4'b1000)
        begin
            $display("FAIL. Check the results.");
            $finish;
        end
 
        $display("SB signals generation successfully tested.");
 
        $display("Testing SH signals generation...");
 
        FUNCT3 = `FUNCT3_HALF;
        RS2 = $random;
        MEM_WR_REQ = 1'b1;
        IADDER_OUT[1:0] = 2'b00;
 
        #10;
 
        if(DATA_OUT != {16'b0, RS2[15:0]})
        begin
            $display("FAIL. Check the results.");
            $finish;
        end
        if(WR_REQ != 1'b1)
        begin
            $display("FAIL. Check the results.");
            $finish;
        end
        if(WR_MASK != 4'b0011)
        begin
            $display("FAIL. Check the results.");
            $finish;
        end
 
        FUNCT3 = `FUNCT3_HALF;
        RS2 = $random;
        MEM_WR_REQ = 1'b1;
        IADDER_OUT[1:0] = 2'b10;
 
        #10;
 
        if(DATA_OUT != {RS2[15:0], 16'b0})
        begin
            $display("FAIL. Check the results.");
            $finish;
        end
        if(WR_REQ != 1'b1)
        begin
            $display("FAIL. Check the results.");
            $finish;
        end
        if(WR_MASK != 4'b1100)
        begin
            $display("FAIL. Check the results.");
            $finish;
        end
 
        $display("SH signals generation successfully tested.");
 
        $display("Testing SW signals generation...");
 
        FUNCT3 = `FUNCT3_WORD;
        RS2 = $random;
        MEM_WR_REQ = 1'b1;
        IADDER_OUT[1:0] = 2'b00;
 
        #10;
 
        if(DATA_OUT != RS2)
        begin
            $display("FAIL. Check the results.");
            $finish;
        end
        if(WR_REQ != 1'b1)
        begin
            $display("FAIL. Check the results.");
            $finish;
        end
        if(WR_MASK != 4'b1111)
        begin
            $display("FAIL. Check the results.");
            $finish;
        end
 
        $display("SW signals generation successfully tested.");
 
        $display("Store Unit successfully tested.");
 
    end
 
endmodule

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Subversion Repositories steelcore

[/] [rtl/] [bench/] [tb_store_unit.v] - Blame information for rev 11

Line No.	Rev	Author	Line
1	11	rafaelcalc	`//////////////////////////////////////////////////////////////////////////////////`
2			`// Engineer: Rafael de Oliveira Calçada (rafaelcalcada@gmail.com)`
3			`//`
4			`// Create Date: 02.06.2020 16:03:55`
5			`// Module Name: tb_store_unit`
6			`// Project Name: Steel Core`
7			`// Description: Store Unit testbench`
8			`//`
9			`// Dependencies: globals.vh`
10			`// store_unit.v`
11			`//`
12			`// Version 0.01`
13			`//`
14			`//////////////////////////////////////////////////////////////////////////////////`
15
16			`/*********************************************************************************`
17
18			`MIT License`
19
20			`Copyright (c) 2020 Rafael de Oliveira Calçada`
21
22			`Permission is hereby granted, free of charge, to any person obtaining a copy`
23			`of this software and associated documentation files (the "Software"), to deal`
24			`in the Software without restriction, including without limitation the rights`
25			`to use, copy, modify, merge, publish, distribute, sublicense, and/or sell`
26			`copies of the Software, and to permit persons to whom the Software is`
27			`furnished to do so, subject to the following conditions:`
28
29			`The above copyright notice and this permission notice shall be included in all`
30			`copies or substantial portions of the Software.`
31
32			`THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR`
33			`IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,`
34			`FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE`
35			`AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER`
36			`LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,`
37			`OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE`
38			`SOFTWARE.`
39
40			`********************************************************************************/`
41
42			`timescale 1ns / 1ps
43			`include "../globals.vh"
44
45
46			`module tb_store_unit();`
47
48			`reg [2:0] FUNCT3;`
49			`reg [31:0] IADDER_OUT;`
50			`reg [31:0] RS2;`
51			`reg MEM_WR_REQ;`
52			`wire [31:0] DATA_OUT;`
53			`wire [31:0] D_ADDR;`
54			`wire [3:0] WR_MASK;`
55			`wire WR_REQ;`
56
57			`store_unit dut(`
58
59			`.FUNCT3(FUNCT3[1:0]),`
60			`.IADDER_OUT(IADDER_OUT),`
61			`.RS2(RS2),`
62			`.MEM_WR_REQ(MEM_WR_REQ),`
63			`.DATA_OUT(DATA_OUT),`
64			`.D_ADDR(D_ADDR),`
65			`.WR_MASK(WR_MASK),`
66			`.WR_REQ(WR_REQ)`
67
68			`);`
69
70			`integer i;`
71
72			`initial`
73			`begin`
74
75			FUNCT3 = `FUNCT3_BYTE;
76			`RS2 = $random;`
77			`MEM_WR_REQ = 1'b0;`
78
79			`$display("Testing D_ADDR generation...");`
80
81			`for(i = 0; i < 20; i=i+1)`
82			`begin`
83
84			`IADDER_OUT = $random;`
85
86			`#10;`
87
88			`if(D_ADDR != {IADDER_OUT[31:2], 2'b00})`
89			`begin`
90			`$display("FAIL. Check the results.");`
91			`$finish;`
92			`end`
93
94			`end`
95
96			`$display("D_ADDR generation OK.");`
97
98			`$display("Testing SB signals generation...");`
99
100			FUNCT3 = `FUNCT3_BYTE;
101			`RS2 = $random;`
102			`MEM_WR_REQ = 1'b1;`
103			`IADDER_OUT[1:0] = 2'b00;`
104
105			`#10;`
106
107			`if(DATA_OUT != {24'b0, RS2[7:0]})`
108			`begin`
109			`$display("FAIL. Check the results.");`
110			`$finish;`
111			`end`
112			`if(WR_REQ != 1'b1)`
113			`begin`
114			`$display("FAIL. Check the results.");`
115			`$finish;`
116			`end`
117			`if(WR_MASK != 4'b0001)`
118			`begin`
119			`$display("FAIL. Check the results.");`
120			`$finish;`
121			`end`
122
123			FUNCT3 = `FUNCT3_BYTE;
124			`RS2 = $random;`
125			`MEM_WR_REQ = 1'b1;`
126			`IADDER_OUT[1:0] = 2'b01;`
127
128			`#10;`
129
130			`if(DATA_OUT != {16'b0, RS2[7:0], 8'b0})`
131			`begin`
132			`$display("FAIL. Check the results.");`
133			`$finish;`
134			`end`
135			`if(WR_REQ != 1'b1)`
136			`begin`
137			`$display("FAIL. Check the results.");`
138			`$finish;`
139			`end`
140			`if(WR_MASK != 4'b0010)`
141			`begin`
142			`$display("FAIL. Check the results.");`
143			`$finish;`
144			`end`
145
146			FUNCT3 = `FUNCT3_BYTE;
147			`RS2 = $random;`
148			`MEM_WR_REQ = 1'b1;`
149			`IADDER_OUT[1:0] = 2'b10;`
150
151			`#10;`
152
153			`if(DATA_OUT != {8'b0, RS2[7:0], 16'b0})`
154			`begin`
155			`$display("FAIL. Check the results.");`
156			`$finish;`
157			`end`
158			`if(WR_REQ != 1'b1)`
159			`begin`
160			`$display("FAIL. Check the results.");`
161			`$finish;`
162			`end`
163			`if(WR_MASK != 4'b0100)`
164			`begin`
165			`$display("FAIL. Check the results.");`
166			`$finish;`
167			`end`
168
169			FUNCT3 = `FUNCT3_BYTE;
170			`RS2 = $random;`
171			`MEM_WR_REQ = 1'b1;`
172			`IADDER_OUT[1:0] = 2'b11;`
173
174			`#10;`
175
176			`if(DATA_OUT != {RS2[7:0], 24'b0})`
177			`begin`
178			`$display("FAIL. Check the results.");`
179			`$finish;`
180			`end`
181			`if(WR_REQ != 1'b1)`
182			`begin`
183			`$display("FAIL. Check the results.");`
184			`$finish;`
185			`end`
186			`if(WR_MASK != 4'b1000)`
187			`begin`
188			`$display("FAIL. Check the results.");`
189			`$finish;`
190			`end`
191
192			`$display("SB signals generation successfully tested.");`
193
194			`$display("Testing SH signals generation...");`
195
196			FUNCT3 = `FUNCT3_HALF;
197			`RS2 = $random;`
198			`MEM_WR_REQ = 1'b1;`
199			`IADDER_OUT[1:0] = 2'b00;`
200
201			`#10;`
202
203			`if(DATA_OUT != {16'b0, RS2[15:0]})`
204			`begin`
205			`$display("FAIL. Check the results.");`
206			`$finish;`
207			`end`
208			`if(WR_REQ != 1'b1)`
209			`begin`
210			`$display("FAIL. Check the results.");`
211			`$finish;`
212			`end`
213			`if(WR_MASK != 4'b0011)`
214			`begin`
215			`$display("FAIL. Check the results.");`
216			`$finish;`
217			`end`
218
219			FUNCT3 = `FUNCT3_HALF;
220			`RS2 = $random;`
221			`MEM_WR_REQ = 1'b1;`
222			`IADDER_OUT[1:0] = 2'b10;`
223
224			`#10;`
225
226			`if(DATA_OUT != {RS2[15:0], 16'b0})`
227			`begin`
228			`$display("FAIL. Check the results.");`
229			`$finish;`
230			`end`
231			`if(WR_REQ != 1'b1)`
232			`begin`
233			`$display("FAIL. Check the results.");`
234			`$finish;`
235			`end`
236			`if(WR_MASK != 4'b1100)`
237			`begin`
238			`$display("FAIL. Check the results.");`
239			`$finish;`
240			`end`
241
242			`$display("SH signals generation successfully tested.");`
243
244			`$display("Testing SW signals generation...");`
245
246			FUNCT3 = `FUNCT3_WORD;
247			`RS2 = $random;`
248			`MEM_WR_REQ = 1'b1;`
249			`IADDER_OUT[1:0] = 2'b00;`
250
251			`#10;`
252
253			`if(DATA_OUT != RS2)`
254			`begin`
255			`$display("FAIL. Check the results.");`
256			`$finish;`
257			`end`
258			`if(WR_REQ != 1'b1)`
259			`begin`
260			`$display("FAIL. Check the results.");`
261			`$finish;`
262			`end`
263			`if(WR_MASK != 4'b1111)`
264			`begin`
265			`$display("FAIL. Check the results.");`
266			`$finish;`
267			`end`
268
269			`$display("SW signals generation successfully tested.");`
270
271			`$display("Store Unit successfully tested.");`
272
273			`end`
274
275			`endmodule`