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[/] [rtl/] [globals.vh] - Blame information for rev 11

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//////////////////////////////////////////////////////////////////////////////////
// Engineer: Rafael de Oliveira Calçada (rafaelcalcada@gmail.com) 
// 
// Create Date: 30.03.2020 17:28:42
// Module Name: -
// Project Name: Steel 
// Description: Steel Core global definitions
// 
// Dependencies: -
// 
// Revision:
// Revision 5.01 - Refactoring #5
// 
//////////////////////////////////////////////////////////////////////////////////
 
/*********************************************************************************
 
MIT License
 
Copyright (c) 2020 Rafael de Oliveira Calçada
 
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
 
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
 
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
 
********************************************************************************/
 
`ifndef GLOBALS_H
`define GLOBALS_H
 
// CSR registers reset values
`define MCYCLE_RESET        32'h00000000
`define TIME_RESET          32'h00000000
`define MINSTRET_RESET      32'h00000000
`define MCYCLEH_RESET       32'h00000000
`define TIMEH_RESET         32'h00000000
`define MINSTRETH_RESET     32'h00000000
`define MTVEC_BASE_RESET    30'b00000000_00000000_00000000_000000
`define MTVEC_MODE_RESET    2'b00
`define MSCRATCH_RESET      32'h00000000
`define MEPC_RESET          32'h00000000
`define MCOUNTINHIBIT_CY_RESET  1'b0
`define MCOUNTINHIBIT_IR_RESET  1'b0
 
// -------------------------------------------------------------------------------
// WARNING: ALL VALUES BELOW MUST NOT BE MODIFIED
// -------------------------------------------------------------------------------
 
// Implemented instructions opcodes
 
`define NOP_INSTR           32'b000000000000_00000_000_00000_0010011
`define OPCODE_OP           5'b01100
`define OPCODE_OP_IMM       5'b00100
`define OPCODE_LOAD         5'b00000
`define OPCODE_STORE        5'b01000
`define OPCODE_BRANCH       5'b11000
`define OPCODE_JAL          5'b11011
`define OPCODE_JALR         5'b11001
`define OPCODE_LUI          5'b01101
`define OPCODE_AUIPC        5'b00101
`define OPCODE_MISC_MEM     5'b00011
`define OPCODE_SYSTEM       5'b11100
 
// funct7 and funct3 for logic and arithmetic instructions
 
`define FUNCT7_SUB          7'b0100000
`define FUNCT7_SRA          7'b0100000
`define FUNCT7_ADD          7'b0000000
`define FUNCT7_SLT          7'b0000000
`define FUNCT7_SLTU         7'b0000000
`define FUNCT7_AND          7'b0000000
`define FUNCT7_OR           7'b0000000
`define FUNCT7_XOR          7'b0000000
`define FUNCT7_SLL          7'b0000000
`define FUNCT7_SRL          7'b0000000
`define FUNCT7_SRAI         7'b0100000
`define FUNCT7_ADDI         7'bxxxxxxx
`define FUNCT7_SLTI         7'bxxxxxxx
`define FUNCT7_SLTIU        7'bxxxxxxx
`define FUNCT7_ANDI         7'bxxxxxxx
`define FUNCT7_ORI          7'bxxxxxxx
`define FUNCT7_XORI         7'bxxxxxxx
`define FUNCT7_SLLI         7'b0000000
`define FUNCT7_SRLI         7'b0000000
 
`define FUNCT3_ADD          3'b000
`define FUNCT3_SUB          3'b000
`define FUNCT3_SLT          3'b010
`define FUNCT3_SLTU         3'b011
`define FUNCT3_AND          3'b111
`define FUNCT3_OR           3'b110
`define FUNCT3_XOR          3'b100
`define FUNCT3_SLL          3'b001
`define FUNCT3_SRL          3'b101
`define FUNCT3_SRA          3'b101
 
// ALU operations encoding
 
`define ALU_ADD          4'b0000
`define ALU_SUB          4'b1000
`define ALU_SLT          4'b0010
`define ALU_SLTU         4'b0011
`define ALU_AND          4'b0111
`define ALU_OR           4'b0110
`define ALU_XOR          4'b0100
`define ALU_SLL          4'b0001
`define ALU_SRL          4'b0101
`define ALU_SRA          4'b1101
 
// funct7 and funct3 for other instructions
 
`define FUNCT7_ECALL        7'b0000000
`define FUNCT7_EBREAK       7'b0000000
`define FUNCT7_MRET         7'B0011000
 
`define FUNCT3_CSRRW        3'b001
`define FUNCT3_CSRRS        3'b010
`define FUNCT3_CSRRC        3'b011
`define FUNCT3_CSRRWI       3'b101
`define FUNCT3_CSRRSI       3'b110
`define FUNCT3_CSRRCI       3'b111
 
`define FUNCT3_BEQ          3'b000
`define FUNCT3_BNE          3'b001
`define FUNCT3_BLT          3'b100
`define FUNCT3_BGE          3'b101
`define FUNCT3_BLTU         3'b110
`define FUNCT3_BGEU         3'b111
 
`define FUNCT3_ECALL        3'b000
`define FUNCT3_EBREAK       3'b000
`define FUNCT3_MRET         3'b000
`define FUNCT3_WFI          3'b000
 
`define FUNCT3_BYTE         3'b000
`define FUNCT3_HALF         3'b001
`define FUNCT3_WORD         3'b010
`define FUNCT3_BYTE_U       3'b100
`define FUNCT3_HALF_U       3'b101
 
// rd, rs1 and rs2 values for SYSTEM instructions
 
`define RS1_ECALL           5'b00000
`define RS1_EBREAK          5'b00000
`define RS1_MRET            5'b00000
`define RS1_WFI             5'b00000
 
`define RS2_ECALL           5'b00000
`define RS2_EBREAK          5'b00001
`define RS2_MRET            5'b00010
`define RS2_WFI             5'b00101
 
`define RD_ECALL            5'b00000
`define RD_EBREAK           5'b00000
`define RD_MRET             5'b00000
`define RD_WFI              5'b00000
 
// writeback selection
`define WB_ALU                 3'b000
`define WB_LU                  3'b001
`define WB_IMM                 3'b010
`define WB_IADDER_OUT          3'b011
`define WB_CSR                 3'b100
`define WB_PC_PLUS             3'b101
 
// immediate format selection
 
`define R_TYPE              3'b000
`define I_TYPE              3'b001
`define S_TYPE              3'b010
`define B_TYPE              3'b011
`define U_TYPE              3'b100
`define J_TYPE              3'b101
`define CSR_TYPE            3'b110
 
// PC MUX selection
 
`define PC_BOOT             2'b00
`define PC_EPC              2'b01
`define PC_TRAP             2'b10
`define PC_NEXT             2'b11
 
// mask for byte-writes
 
`define WR_MASK_BYTE          4'b0001
`define WR_MASK_HALF          4'b0011
`define WR_MASK_WORD          4'b1111
 
// load unit control encoding
 
`define LOAD_BYTE          2'b00
`define LOAD_HALF          2'b01
`define LOAD_WORD          2'b10
 
// CSR File operation encoding
 
`define CSR_NOP            2'b00
`define CSR_RW             2'b01
`define CSR_RS             2'b10
`define CSR_RC             2'b11
 
// CSR ADDRESSES ----------------------------
 
// Performance Counters
`define CYCLE           12'hC00
`define TIME            12'hC01
`define INSTRET         12'hC02
`define CYCLEH          12'hC80
`define TIMEH           12'hC81
`define INSTRETH        12'hC82
 
// Machine Trap Setup
`define MSTATUS         12'h300
`define MISA            12'h301
`define MIE             12'h304
`define MTVEC           12'h305
 
// Machine Trap Handling
`define MSCRATCH        12'h340
`define MEPC            12'h341
`define MCAUSE          12'h342
`define MTVAL           12'h343
`define MIP             12'h344
 
// Machine Counter / Timers
`define MCYCLE          12'hB00
`define MINSTRET        12'hB02
`define MCYCLEH         12'hB80
`define MINSTRETH       12'hB82
 
// Machine Counter Setup
`define MCOUNTINHIBIT   12'h320
 
`endif

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Subversion Repositories steelcore

[/] [rtl/] [globals.vh] - Blame information for rev 11

Line No.	Rev	Author	Line
1	11	rafaelcalc	`//////////////////////////////////////////////////////////////////////////////////`
2			`// Engineer: Rafael de Oliveira Calçada (rafaelcalcada@gmail.com)`
3			`//`
4			`// Create Date: 30.03.2020 17:28:42`
5			`// Module Name: -`
6			`// Project Name: Steel`
7			`// Description: Steel Core global definitions`
8			`//`
9			`// Dependencies: -`
10			`//`
11			`// Revision:`
12			`// Revision 5.01 - Refactoring #5`
13			`//`
14			`//////////////////////////////////////////////////////////////////////////////////`
15
16			`/*********************************************************************************`
17
18			`MIT License`
19
20			`Copyright (c) 2020 Rafael de Oliveira Calçada`
21
22			`Permission is hereby granted, free of charge, to any person obtaining a copy`
23			`of this software and associated documentation files (the "Software"), to deal`
24			`in the Software without restriction, including without limitation the rights`
25			`to use, copy, modify, merge, publish, distribute, sublicense, and/or sell`
26			`copies of the Software, and to permit persons to whom the Software is`
27			`furnished to do so, subject to the following conditions:`
28
29			`The above copyright notice and this permission notice shall be included in all`
30			`copies or substantial portions of the Software.`
31
32			`THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR`
33			`IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,`
34			`FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE`
35			`AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER`
36			`LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,`
37			`OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE`
38			`SOFTWARE.`
39
40			`********************************************************************************/`
41
42			`ifndef GLOBALS_H
43			`define GLOBALS_H
44
45			`// CSR registers reset values`
46			`define MCYCLE_RESET 32'h00000000
47			`define TIME_RESET 32'h00000000
48			`define MINSTRET_RESET 32'h00000000
49			`define MCYCLEH_RESET 32'h00000000
50			`define TIMEH_RESET 32'h00000000
51			`define MINSTRETH_RESET 32'h00000000
52			`define MTVEC_BASE_RESET 30'b00000000_00000000_00000000_000000
53			`define MTVEC_MODE_RESET 2'b00
54			`define MSCRATCH_RESET 32'h00000000
55			`define MEPC_RESET 32'h00000000
56			`define MCOUNTINHIBIT_CY_RESET 1'b0
57			`define MCOUNTINHIBIT_IR_RESET 1'b0
58
59			`// -------------------------------------------------------------------------------`
60			`// WARNING: ALL VALUES BELOW MUST NOT BE MODIFIED`
61			`// -------------------------------------------------------------------------------`
62
63			`// Implemented instructions opcodes`
64
65			`define NOP_INSTR 32'b000000000000_00000_000_00000_0010011
66			`define OPCODE_OP 5'b01100
67			`define OPCODE_OP_IMM 5'b00100
68			`define OPCODE_LOAD 5'b00000
69			`define OPCODE_STORE 5'b01000
70			`define OPCODE_BRANCH 5'b11000
71			`define OPCODE_JAL 5'b11011
72			`define OPCODE_JALR 5'b11001
73			`define OPCODE_LUI 5'b01101
74			`define OPCODE_AUIPC 5'b00101
75			`define OPCODE_MISC_MEM 5'b00011
76			`define OPCODE_SYSTEM 5'b11100
77
78			`// funct7 and funct3 for logic and arithmetic instructions`
79
80			`define FUNCT7_SUB 7'b0100000
81			`define FUNCT7_SRA 7'b0100000
82			`define FUNCT7_ADD 7'b0000000
83			`define FUNCT7_SLT 7'b0000000
84			`define FUNCT7_SLTU 7'b0000000
85			`define FUNCT7_AND 7'b0000000
86			`define FUNCT7_OR 7'b0000000
87			`define FUNCT7_XOR 7'b0000000
88			`define FUNCT7_SLL 7'b0000000
89			`define FUNCT7_SRL 7'b0000000
90			`define FUNCT7_SRAI 7'b0100000
91			`define FUNCT7_ADDI 7'bxxxxxxx
92			`define FUNCT7_SLTI 7'bxxxxxxx
93			`define FUNCT7_SLTIU 7'bxxxxxxx
94			`define FUNCT7_ANDI 7'bxxxxxxx
95			`define FUNCT7_ORI 7'bxxxxxxx
96			`define FUNCT7_XORI 7'bxxxxxxx
97			`define FUNCT7_SLLI 7'b0000000
98			`define FUNCT7_SRLI 7'b0000000
99
100			`define FUNCT3_ADD 3'b000
101			`define FUNCT3_SUB 3'b000
102			`define FUNCT3_SLT 3'b010
103			`define FUNCT3_SLTU 3'b011
104			`define FUNCT3_AND 3'b111
105			`define FUNCT3_OR 3'b110
106			`define FUNCT3_XOR 3'b100
107			`define FUNCT3_SLL 3'b001
108			`define FUNCT3_SRL 3'b101
109			`define FUNCT3_SRA 3'b101
110
111			`// ALU operations encoding`
112
113			`define ALU_ADD 4'b0000
114			`define ALU_SUB 4'b1000
115			`define ALU_SLT 4'b0010
116			`define ALU_SLTU 4'b0011
117			`define ALU_AND 4'b0111
118			`define ALU_OR 4'b0110
119			`define ALU_XOR 4'b0100
120			`define ALU_SLL 4'b0001
121			`define ALU_SRL 4'b0101
122			`define ALU_SRA 4'b1101
123
124			`// funct7 and funct3 for other instructions`
125
126			`define FUNCT7_ECALL 7'b0000000
127			`define FUNCT7_EBREAK 7'b0000000
128			`define FUNCT7_MRET 7'B0011000
129
130			`define FUNCT3_CSRRW 3'b001
131			`define FUNCT3_CSRRS 3'b010
132			`define FUNCT3_CSRRC 3'b011
133			`define FUNCT3_CSRRWI 3'b101
134			`define FUNCT3_CSRRSI 3'b110
135			`define FUNCT3_CSRRCI 3'b111
136
137			`define FUNCT3_BEQ 3'b000
138			`define FUNCT3_BNE 3'b001
139			`define FUNCT3_BLT 3'b100
140			`define FUNCT3_BGE 3'b101
141			`define FUNCT3_BLTU 3'b110
142			`define FUNCT3_BGEU 3'b111
143
144			`define FUNCT3_ECALL 3'b000
145			`define FUNCT3_EBREAK 3'b000
146			`define FUNCT3_MRET 3'b000
147			`define FUNCT3_WFI 3'b000
148
149			`define FUNCT3_BYTE 3'b000
150			`define FUNCT3_HALF 3'b001
151			`define FUNCT3_WORD 3'b010
152			`define FUNCT3_BYTE_U 3'b100
153			`define FUNCT3_HALF_U 3'b101
154
155			`// rd, rs1 and rs2 values for SYSTEM instructions`
156
157			`define RS1_ECALL 5'b00000
158			`define RS1_EBREAK 5'b00000
159			`define RS1_MRET 5'b00000
160			`define RS1_WFI 5'b00000
161
162			`define RS2_ECALL 5'b00000
163			`define RS2_EBREAK 5'b00001
164			`define RS2_MRET 5'b00010
165			`define RS2_WFI 5'b00101
166
167			`define RD_ECALL 5'b00000
168			`define RD_EBREAK 5'b00000
169			`define RD_MRET 5'b00000
170			`define RD_WFI 5'b00000
171
172			`// writeback selection`
173			`define WB_ALU 3'b000
174			`define WB_LU 3'b001
175			`define WB_IMM 3'b010
176			`define WB_IADDER_OUT 3'b011
177			`define WB_CSR 3'b100
178			`define WB_PC_PLUS 3'b101
179
180			`// immediate format selection`
181
182			`define R_TYPE 3'b000
183			`define I_TYPE 3'b001
184			`define S_TYPE 3'b010
185			`define B_TYPE 3'b011
186			`define U_TYPE 3'b100
187			`define J_TYPE 3'b101
188			`define CSR_TYPE 3'b110
189
190			`// PC MUX selection`
191
192			`define PC_BOOT 2'b00
193			`define PC_EPC 2'b01
194			`define PC_TRAP 2'b10
195			`define PC_NEXT 2'b11
196
197			`// mask for byte-writes`
198
199			`define WR_MASK_BYTE 4'b0001
200			`define WR_MASK_HALF 4'b0011
201			`define WR_MASK_WORD 4'b1111
202
203			`// load unit control encoding`
204
205			`define LOAD_BYTE 2'b00
206			`define LOAD_HALF 2'b01
207			`define LOAD_WORD 2'b10
208
209			`// CSR File operation encoding`
210
211			`define CSR_NOP 2'b00
212			`define CSR_RW 2'b01
213			`define CSR_RS 2'b10
214			`define CSR_RC 2'b11
215
216			`// CSR ADDRESSES ----------------------------`
217
218			`// Performance Counters`
219			`define CYCLE 12'hC00
220			`define TIME 12'hC01
221			`define INSTRET 12'hC02
222			`define CYCLEH 12'hC80
223			`define TIMEH 12'hC81
224			`define INSTRETH 12'hC82
225
226			`// Machine Trap Setup`
227			`define MSTATUS 12'h300
228			`define MISA 12'h301
229			`define MIE 12'h304
230			`define MTVEC 12'h305
231
232			`// Machine Trap Handling`
233			`define MSCRATCH 12'h340
234			`define MEPC 12'h341
235			`define MCAUSE 12'h342
236			`define MTVAL 12'h343
237			`define MIP 12'h344
238
239			`// Machine Counter / Timers`
240			`define MCYCLE 12'hB00
241			`define MINSTRET 12'hB02
242			`define MCYCLEH 12'hB80
243			`define MINSTRETH 12'hB82
244
245			`// Machine Counter Setup`
246			`define MCOUNTINHIBIT 12'h320
247
248			`endif