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URL https://opencores.org/ocsvn/rv01_riscv_core/rv01_riscv_core/trunk

Subversion Repositories rv01_riscv_core

[/] [rv01_riscv_core/] [trunk/] [SIM/] [MODELSIM/] [compile_rv01_selftest.do] - Blame information for rev 2

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1 2 madsilicon 
#-----------------------------------------------------------------
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#--                                                             --
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#-----------------------------------------------------------------
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#--                                                             --
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#-- Copyright (C) 2017 Stefano Tonello                          --
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#--                                                             --
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#-- This source file may be used and distributed without        --
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#-- restriction provided that this copyright statement is not   --
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#-- removed from the file and that any derivative work contains --
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#-- the original copyright notice and the associated disclaimer.--
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#--                                                             --
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#-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY         --
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#-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   --
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#-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   --
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#-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      --
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#-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         --
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#-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    --
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#-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   --
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#-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        --
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#-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  --
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#-- LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  --
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#-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  --
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#-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         --
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#-- POSSIBILITY OF SUCH DAMAGE.                                 --
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#--                                                             --
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#-----------------------------------------------------------------
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#---------------------------------------------------------------
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# RV01 self-test module simulation script for Modelsim
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# simulator.
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#---------------------------------------------------------------
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set SRC_DIR ../../VHDL
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# -----------------------------------------
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# Packages
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# -----------------------------------------
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vcom $SRC_DIR/RV01_consts_pkg.vhd
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vcom $SRC_DIR/RV01_types_pkg.vhd
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vcom $SRC_DIR/RV01_funcs_pkg.vhd
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vcom $SRC_DIR/RV01_arith_pkg.vhd
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vcom $SRC_DIR/RV01_op_pkg.vhd
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vcom $SRC_DIR/RV01_csr_pkg.vhd
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vcom $SRC_DIR/RV01_idec_pkg.vhd
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vcom $SRC_DIR/RV01_div_funcs_pkg.vhd
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vcom $SRC_DIR/RV01_plic_pkg.vhd
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# -----------------------------------------
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# Configuration package
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# -----------------------------------------
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vcom $SRC_DIR/SELF_TEST/RV01_cfg_dhrystone_sodor_st_pkg.vhd
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# -----------------------------------------
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# VHDL code
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# -----------------------------------------
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vcom $SRC_DIR/RV01_adder_f.vhd
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vcom $SRC_DIR/RV01_ftchlog_1w.vhd
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vcom $SRC_DIR/RV01_ftchlog_2w.vhd
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vcom $SRC_DIR/RV01_idec.vhd
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vcom $SRC_DIR/RV01_ifq.vhd
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vcom $SRC_DIR/RV01_pstllog_2w_p6.vhd
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vcom $SRC_DIR/RV01_isslog.vhd
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vcom $SRC_DIR/RV01_mulu.vhd
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vcom $SRC_DIR/RV01_shftu.vhd
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vcom $SRC_DIR/RV01_logicu.vhd
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vcom $SRC_DIR/RV01_pipe_a.vhd
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vcom $SRC_DIR/RV01_pipe_b.vhd
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vcom $SRC_DIR/RV01_lsu.vhd
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vcom $SRC_DIR/RV01_sbuf_2w.vhd
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vcom $SRC_DIR/RV01_regfile_32x32_2w.vhd
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vcom $SRC_DIR/RV01_rams.vhd
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vcom $SRC_DIR/RV01_bjxlog.vhd
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vcom $SRC_DIR/RV01_bjxlog_bv.vhd
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vcom $SRC_DIR/RV01_bht.vhd
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vcom $SRC_DIR/RV01_bpu.vhd
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vcom $SRC_DIR/RV01_pxlog.vhd
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vcom $SRC_DIR/RV01_fwdlog_2w_p6.vhd
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vcom $SRC_DIR/RV01_lzdu.vhd
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vcom $SRC_DIR/RV01_divlog.vhd
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vcom $SRC_DIR/RV01_divider_r2.vhd
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vcom $SRC_DIR/RV01_csru.vhd
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vcom $SRC_DIR/RV01_comp32.vhd
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vcom $SRC_DIR/RV01_dimslog.vhd
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vcom $SRC_DIR/RV01_excplog_ix1.vhd
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vcom $SRC_DIR/RV01_excplog_ix2.vhd
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vcom $SRC_DIR/RV01_excplog_ix3.vhd
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vcom $SRC_DIR/RV01_dbglog_ix2.vhd
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vcom $SRC_DIR/RV01_hltlog_ix2.vhd
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# -----------------------------------------
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# Debug module (not used by self-test module)
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# -----------------------------------------
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#vcom $SRC_DIR/RV01_dbgu.vhd
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vcom $SRC_DIR/RV01_hltu.vhd
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vcom $SRC_DIR/RV01_resmux_ix1.vhd
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vcom $SRC_DIR/RV01_resmux_ix2.vhd
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vcom $SRC_DIR/RV01_resmux_ix3.vhd
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vcom $SRC_DIR/RV01_cdcomux.vhd
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vcom $SRC_DIR/RV01_misclog_ix3.vhd
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vcom $SRC_DIR/RV01_stack.vhd
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vcom $SRC_DIR/RV01_queue.vhd
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vcom $SRC_DIR/RV01_jrpu.vhd
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# -----------------------------------------
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# PLIC module (not used by self-test module)
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# -----------------------------------------
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#vcom $SRC_DIR/RV01_plic_gway.vhd
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#vcom $SRC_DIR/RV01_plic_core.vhd
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#vcom $SRC_DIR/RV01_plic.vhd
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vcom $SRC_DIR/RV01_cpu_init.vhd
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vcom $SRC_DIR/RV01_cpu_2w_p6.vhd
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vcom $SRC_DIR/RV01_top.vhd
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vcom $SRC_DIR/RV01_top_nohost.vhd
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# -----------------------------------------
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# Self-Test module & test-bench
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# -----------------------------------------
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vcom $SRC_DIR/SELF_TEST/dhrystone_sodor_st_rom.vhd
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vcom $SRC_DIR/SELF_TEST/RV01_selftest.vhd
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vcom $SRC_DIR/SELF_TEST/RV01_selftest_TB.vhd
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vsim work.rv01_selftest_tb
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# -----------------------------------------
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# Waveforms
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# -----------------------------------------
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add wave /rv01_selftest_tb/clk
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add wave /rv01_selftest_tb/rst
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add wave /rv01_selftest_tb/done
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add wave /rv01_selftest_tb/pass
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run 1.1ms
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