URL
https://opencores.org/ocsvn/rv01_riscv_core/rv01_riscv_core/trunk
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Line No. |
Rev |
Author |
Line |
1 |
5 |
madsilicon |
create_clock -period 10.000 -name CLK_100M_i -waveform {0.000 5.000} [get_ports CLK_100M_i]
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2 |
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set_property IOSTANDARD LVCMOS33 [get_ports DONE_o]
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3 |
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set_property IOSTANDARD LVCMOS33 [get_ports CLK_100M_i]
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4 |
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set_property IOSTANDARD LVCMOS33 [get_ports PASS_o]
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5 |
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set_property IOSTANDARD LVCMOS33 [get_ports RSTN_i]
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6 |
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set_property IOSTANDARD LVCMOS33 [get_ports TIE_HIGH_o]
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7 |
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set_property IOSTANDARD LVCMOS33 [get_ports TIE_LOW_o]
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8 |
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set_property PACKAGE_PIN E3 [get_ports CLK_100M_i]
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9 |
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set_property PACKAGE_PIN T6 [get_ports TIE_HIGH_o]
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10 |
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11 |
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set_property PACKAGE_PIN C12 [get_ports RSTN_i]
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12 |
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set_property PACKAGE_PIN T8 [get_ports DONE_o]
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13 |
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set_property PACKAGE_PIN V9 [get_ports PASS_o]
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14 |
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set_property PACKAGE_PIN R8 [get_ports TIE_LOW_o]
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15 |
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16 |
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set_false_path -from [get_ports RSTN_i]
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17 |
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set_false_path -to [get_ports {TIE_HIGH_o TIE_LOW_o}]
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