Subversion Repositories rv01_riscv_core

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-- RV01: simulation & synthesis VHDL files         --

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This folder includes all VHDL source files required

by RV01 core.

VHDL packages (stored in RV01_*_pkg.vhd files) are

used to define data types and constants that are not

user-modifiable (like, for instance, word width).

All parameters that are user-modifiable get passed

through top-level module generics, in order to allow

every core instance to be configured independently

from the other ones.

The files actually needed to perform a simulation or

synthesis run depend by the core configuration

specified through the top-level module generics.

File RV01_jrpu.vhd, for instance, is needed only if

generic JRPU_PRESENT is set to '1'.

The modules RV01_ST_CHECKER, RV01_WB_CHECKER and

RV01_STATS are referenced by module RV01_CPU_2W_P6

but are not actually needed, as their instantiation

is disabled by generic SIMULATION_ONLY being set to

'0', as required by core documentation.

If simulation/synthesis tool complains about these

modules to be missing, please check generic

SIMULATION_ONLY setting.

The RV01 top-level module is RV01_TOP from file

RV01_top.vhd.

An alternative top-level module is RV01_TOP_NOHOST

from file RV01_top_nohost.vhd.

This module exists mainly as a debugging and

simulation aid, it consists of an instance of the

top-level module RV01_TOP with the MTOHOST_o output

looping back to the MFROMHOST_i and EI_REQ_i inputs.

This arrangement allows to simulate the host interface

and, to some degree, PLIC module operations without

additional logic.

All module and signal names use uppercase letters only,

except for the suffixes described below here.

Signals input to a module have a "_i" suffix appended

to their name, signals output from a module have a "_o"

suffix, while signals internal to a module and driven

by a register, have a "_q" suffix. Signals names without

one of these suffixes are internal to a module and

generated by combinatorial logic.